SANTA CLARA, Calif. Five "discontinuities" that may lead to explosive EDA growth were highlighted in a keynote speech by Wally Rhines, Mentor Graphics president and chief executive, at this week's DesignCon 2001 conference. What may be most controversial, however, is Rhines' belief that physical synthesis one of the hottest topics in EDA does not represent a discontinuity.
Rhines described discontinuities as profound shifts in design methodology, such as the move from schematics to HDL design. He said discontinuities are occurring today in FPGA design, pc-board design, system-on-chip (SoC) verification, analog/mixed-signal design and physical verification. Although Rhines did not discuss Mentor products, Mentor is offering solutions in all five areas.
When existing solutions stop working, these discontinuities occur, said Rhines. "The time to adopt a new tool is when what you have breaks," he said. "That's when changes occur and new technologies enter the market. I've become convinced that a large number of things are reaching the breaking point today."
Rhines said that discontinuities should be distinguished from evolutionary changes, saying that new physical synthesis and physical design solutions from vendors such as Magma, Monterey, Silicon Perspective, Synopsys and others really represent "evolutionary" improvements in the way synthesis works with placement.
Designers aren't going to throw away their existing synthesis and layout tools to embrace new RTL-to-layout solutions. "The industry doesn't go that way," he said. "You can't replace half the tool flow overnight."
But FPGA design, according to Rhines, does represent a true discontinuity. "When you get close to a million gates, the old tools for FPGAs start to break," he said. This, he said, opens an opportunity to bring ASIC-like synthesis and simulation tools to FPGA designers. But it's not so easy, he noted, because FPGAs are dominated by interconnect delays, and because each FPGA architecture requires its own specialized router.
Cost is another barrier. "We now have people who need the same capabilities as an ASIC designer, but who are used to paying $10,000 for a complete toolset," Rhines said. "That means we need to find a whole new way to serve a new industry."
In pc-board design, a "strange thing is happening," Rhines said. He noted that this previously slow-growth market has been outstripping overall EDA product growth during the past four quarters. The reason, said Rhines, is that technology is changing. With 20-layer boards, 20-mil traces, blind and buried vias, and all the challenges of high-speed design, boards are becoming a "critical bottleneck" in the design process, he said.
SoC verification has already been recognized as a crisis by many observers. Rhines called it a discontinuity that will result "in a return to hardware, in a sense going back to the days of prototyping." He emphasized the importance of simulation acceleration, emulation, and virtual prototyping systems.
In the analog/mixed-signal area, Rhines said, the lack of designers is increasing. He noted that people are trying to figure out how to implement analog features in low-cost digital CMOS. As a result, Rhines said, tools that support analog/mixed-signal simulation and languages such as Verilog-AMS are suddenly gaining popularity.
Physical verification is an area that "broke" about four years ago, Rhines said, due to the increasing size of designs. "The need for hierarchy and parallel processing are driving a physical verification discontinuity," he said. Rhines didn't push his company's Calibre hierarchical physical verification tool, but it's one of Mentor's most successful offerings, and it claims to handle extremely large IC designs.