SUNNYVALE, Calif.-- Mitsubishi Electric Corp.'s chip subsidiary here today (March 28) announced a new series of low-power synchronous DRAMs that contain a number of battery-saving features for handheld and wireless system products.
The first member in Mitsubishi's new LP-SDRAM series is a 64-megabit chip, configured as a 4-Mbit-by-16-bit memory. The low-power SDRAM is fabricated with a 0.18-micron process technology. It will be available in a 54-contact ball-grid array (BGA) package as well as a 64-pin shrink thin small outline package (STSOP).
The LP-SDRAM family reduces power consumption with a memory array that operates at 2.5 volts and I/O interfaces using 1.8 volts. Mitsubishi said it will also produce variations of the memory design based on customer requirements for power supplies.
Other battery-saving features in the SDRAM include a "partial array self-refresh" and "deep power down" functions. The 64-Mbit LP-SDRAM achieves a 300-microA self-refresh current for the entire array, which is about 40% less than conventional SDRAMs, according to the Japanese chip maker.
Samples of the 64-Mbit LP-SDRAM will be available in July. The 64-pin STSOP version will be available first, followed by the BGA memory in September. Volume production is scheduled to begin in the fourth quarter of 2001. Sample pricing is $15 for the STSOP version and $17 for the BGA-packaged memory.