SANTA CLARA, Calif. -- In a move to accelerate sub-micron chip designs, NEC Electronics Inc. announced that it will offer Tera Systems Inc.'s timing and layout EDA tools in its ASIC libraries.
Under the plan, NEC will offer Tera's TeraGate libraries in its 0.25- and 0.18-micron process. TeraGate enables the use of Tera's register-transfer-level (RTL) design planning tool. Dubbed TeraForm, the tool enables designers to identify and correct RTL code that will cause downstream gate-level timing and layout congestion problems.
NEC will release these libraries for its 0.25-micron CBC-10, 0.25-micron CBC-10VX, and 0.18-micron CB-11 ASIC process technologies. It will also develop a TeraGate library for its state-of-the-art 0.13-micron CB-12 process as well.
"This announcement reinforces our commitment to move the design engagement to the register-transfer-level," said Kazu Yamada, general manager of NEC's Technology Foundation Group. "By enabling timing and area analyses earlier in the design phase with the TeraForm system, our customers can count on greater flow predictability and shorter design turnaround times," he said.
"We intend to use the TeraGate libraries with designs in the multi-million-gate range," said Hiroshi Sakuma, assistant general manager in NEC's Technology Foundation Group. "TeraForm can partition and floorplan the designs automatically, identify critical paths by analyzing full-chip timing, and drive our back-end tools to timing closure more rapidly and with less effort on our part."