SAN JOSE -- Attempting to play catch up in the market, the SigmaRAM Consortium next month will finally unveil its roadmap and first wave of SRAM products for high-performance networking applications.
On June 18, the members of consortium--GSI Technology, ISSI, Mitsubishi, Sony, and Toshiba--will each present detailed technical specifications for three common I/O and three separate I/O SRAM memories conforming to the SigmaRAM specification.
SigmaRAM devices are JEDEC-approved static random access memories designed to provide sustained throughput rates of 24-gigabits-per-second in both SDRAM anddouble data rate SDRAM formats. The memories will come in 209-contact ball-grid array (BGA) packages.
The SigmaRAM group won standardization last year from the Joint Electronic Devices Engineering Council (JEDEC). But a competing camp of memory makers is also pushing its standard--the Quad Data Rate (QDR) SRAM--for networking applications. The QDR format has gotten a head start in the market with the availability of chips offering 8 megabits of storage.
The QDR camp includes Cypress, Integrated Device Technology, Micron, NEC,
and Samsung, which joined the group last month (see April 2 story).
The QDR and SigmaRAM groups differ in their approaches. The SigmaRAM group supports a larger package that could accept 18-Mbit, 32-Mbit and larger densities. The QDR group supports a less aggressive package that is adequate for the 8/9-Mbit, and 6/18-Mbit densities.