SAN JOSE --Cypress Semiconductor Corp. here today claimed to be the first to offer a programmable chip solution for physical layer (PHY) interface to synchronous digital hierarchy/synchronous optical networks (SDH/Sonet) operating at 2.5-gigabit-per-second OC-48 rates.
The PSI2G100S integrates an OC-48 transceiver, clock data recovery (CDR) circuitry, a Serializer/Deserializer (SerDes), 100,000 gates of programmable logic, and 240 kilobits of communications memory. The IC is aimed at OC-48/STM-12 optical terminators, Sonet/SDH routers and add-drop MUX subsystems.
"The PSI2G100S brings the speed and flexibility of our programmable OC-48 SerDes to Sonet/SDH applications," said Geoff Charubin, director of marketing for the Data Communications Division at Cypress. He said the integration of programmable logic and other functions will enable system designers to speed development of optical networking solutions for wide-area networks using OC-48 data rates.
According to Cypress, the PSI2G100S is suited for both port and backplane solutions in a typical line card application. The device's programmable feature enables system manufacturers to create customized and flexible solutions for the parallel-side interface, said the company. An example of this type of interface application is a system that receives OC-48 data from the serial side and converts it to a 32- or 64-bit parallel-bus topology.
Housed in a 456-contact ball-grid array (BGA), the PSI2G100S is priced at $150 each in production-quantity volumes. Samples are available now.