GENEVA--STMicroelectronics today announced samples of a new CMOS read/write channel chip that supports data rates up to 750 megabits per second and features advanced signal processing techniques for wider tolerance of heads and media.
The "Bramante" IC, designated L6363, is fabricated in a 0.18-micron technology, which STMicroelectronics said is a "pure" CMOS process rather than a mixture of bipolar and CMOS--BiCMOS. The application of pure CMOS processes to read/write channel designs allow future integration of other drive functions to the devices, said the European semiconductor maker.
The current design integrates a Partial Response Maximum Likelihood (PRML) read channel with a self-adaptive media noise cancellation scheme, called Media Noise Terminator, said STMicroelectronics. The noise cancellation technique ensures optimum performance over a wide range of data densities and different noise conditions, according to the company.
The detector in the Bramante chip is a 16-state Trellis-Viterbi, matched to the channel code. ST said a high rate 16/17 MTR code or a lower rate 304/338 code with Enhanced Parity can be chosen by the drive designer to obtain higher speed or better noise performance.
"By offering a fully functional high-performance CMOS read channel we enable a higher level of system-on-chip integration for our customers -- the key to reducing system cost in the high-volume hard disk drive market," said Franco Berenga, General Manager of STMicroelectronics' Data Storage Division. "In addition, it is possible to increase the level of miniaturization for the mobile market, including the emerging microdrive, and to improve the system-on-chip performance by optimal partitioning between the different blocks integrated into a single device."
ST said it was now sampling the L6363 chip, but did not release pricing information for volume shipments.