PALO ALTO, Calif. -- During the annual Hot Chips Conference at Stanford University here in mid-August, Intel Corp. plans to disclose more details about its Pentium 4 and Itanium processor series as well as the awaited 870 chip set, which will support double data rate (DDR) synchronous DRAMs in computer servers. The 870 will also support Direct Rambus DRAMs.
Also at the conference, IBM Corp. is slated to describe its new Power4 processor, which will have more than 170 million transistors and will be targeted at frequencies over 1 GHz. IBM will also present information on a custom-designed PowerPC derivative, called "Gekko," for video game consoles. ARM Ltd. will present details on its ARM10 RISC core series, and PMC-Sierra Inc. plans to describe a 2.5 terabyte-per-second single-stage packet switch, called "Tiny Tera-X."
Other presentations are planned by Qualcomm, Hitachi, Agere Systems, Toshiba, and others, said the conference organizers. The Hot Chips Conference is set for Aug. 19-13.
Intel is expected to describe the main features and functions of its Pentium 4 micro-architecture, which uses a new form of instruction cache, called "Execution Trace Cache." It also features an out-of-order execution engine, including an extremely low latency double-pumped arithmetic logic unit (ALU) that runs at more than 3.4 GHz, according to information release by the conference organizer today.
The 870 will have a highly scalable port as part of the North Bridge. It will support both Intel's 64-bit Itanium microprocessors and the IA32 Xeon central processing units. The chip set will support 1 to 16 coherent processors and contain what Intel describes as a "robust RAS features, including multipathing, node hot plug, static and dynamic partitioning, said the Hot Chips organizer.
IBM's Server Group will describe the Power4 chip, which is based on the company's 0.18-micron CMOS silicon-on-insulator (SOI) technology with seven layers of copper interconnect. The chip contains two independent out-of-order processor cores, each with eight execution units, a shared L2 and L3 directory and logic for large symmetric multiprocessor systems, according to information released today. More than 200 instructions can be in various stages of execution in the Power4 chip.
IBM's Microelectronics Division is scheduled to present information about PowerPC-based Gekko processor, aimed at video game consoles. It will provide general-purpose processing performance exceeding 1,000 DMIPS, according to information released today. ISA extensions will support increased floating-point throughput, streaming data for models and graphics, and data compression, based on material to be presented at the conference.
PMC-Sierra's Tiny Tera-X is a 2.5 terabit-per-second single-stage, centrally arbitrated switch core with linecard-to-switch (LCS) interfaces. The switch can interconnect up to 1,024 linecards each operating at 2.5 gigabit-per-second (OC48), 256 linecards 10 Gb/s (OC192), 64 linecards at 40 Gb/s (OC768), or any mixture up to a maximum full-duplex capacity of 2.5 Tb/s, according to the Hot Chips Conference. (Editor's note: the conference corrected the speed of the switch in an early release of this information from 2.5 terabytes/sec. to terabits/sec.)