SAN JOSE -- Cypress Semiconductor, Integrated Device Technology, Micron, NEC, and Samsung today announced enhancements to the Quad Data Rate (QDR) architecture for SRAMs, pushing the overall memory performance to 333-MHz clock speeds.
The initial 18-megabit SRAM, based on the QDR enhancements, is now under development, and samples of prototypes are expected by the fourth quarter, said the group. The five SRAM makers cooperated in developing the enhancements, which are now called QDRII/DDR II (Double Data Rate).
"This milestone of producing first silicon, reinforces the co-development team's commitment to meet the roadmap schedules," said Mario Martinez, director of strategic marketing for the Memory Products Division of Cypress in San Jose.
The QDR cooperative was launched in 1999 as a partnership between Cypress, IDT and Micron to define static RAMs for switches and routers that operated at data rates above 200 MHz (see July 26, 1999, story). The group expanded this year with the addition of NEC Corp. and Samsung Electronics Co. Ltd.
The enhanced QDRII architecture has been designed to provide customers with "an expected data valid window of 65% of the clock cycle" while operating at 333 MHz, said J. Thomas Pawlowski, senior fellow at Micron Technology Inc. in Boise, Idaho. The architecture allows designers to avoid the possibility of bus contention while systems are operating at high speed.
Next week, a competing group--called the SigmaRAM Consortium--is expected to unveil its roadmap and first wave of high-speed SRAMs (see May 31 story). This group is made of GSI Technology, ISSI, Mitsubishi, Sony, and Toshiba.
But the QDR camp believes its new architecture has a number of advantages over other approaches in speeding up SRAMs for communications and high-speed systems. For one thing, the QDR co-development team said it has optimized the IC packaging for Quad Data Rate memories. A 13-mm-by-15-mm FBGA package is used with 165-ball contacts. This package has been defined for 18-, 36-, and 72-Mbit chip densities, said the group.
"Our packaging strategy focused on meeting three key objectives our customers require: space savings, performance migration, and cost reduction," said Mike Black, strategic SRAM marketing manager at Micron.
"The 165-pin FBGA provides customers the flexibility to design for future density and performance migrations while achieving a 40% space savings gained over traditional 209-ball, 14-mm--by-22-mm BGA, or 100-pin TQFP packages," he said. "Equally important, the new FBGA is designed for clamshell applications," added Black, referring to space-constrained portable system designs.