CHANDLER, Ariz.-- Microchip Technology Inc. here today announced a chip architecture for 16-bit digital signal controllers which will combine the performance of 16-bit microcontrollers with the computational speeds of digital signal processors (DSPs) for embedded system designs.
The new core, called dsPIC, is a 16-bit non-pipelined modified Harvard RISC machine which is designed to deliver "a tightly coupled, single-chip single-instruction stream solution for embedded system designs," said the Chandler company. The DSP instructions operate seamlessly with all other instructions, said Microchip, and these instructions have been designed for optimal real-time performance.
Microchip said the dsPIC architecture is capable of handling 30 million instructions per second (MIPS), making it suitable for high-performance 16-bit MCU applications as well as "moderate-performance" DSP jobs in motor control, soft modems, automotive body computers, speech recognition, echo cancellation, and fingerprint recognition.
The company said it has developed a novel "dynamically reconfigurable data memory architecture" that helps to maintain a microcontroller "look and feel" by allowing MCU instructions to use data space in a conventional approach while preserving the data memory access bandwidth required by DSP operations.
The architecture supports up to 4-megabytes-by-24-bit addressable Flash program memory space and up to 32-Kbyte-by-16 data space, said the company. The MCU/DSP combo architecture operates on a 2.5-to-5.5-V supply. Products based on the architecture are expected to be housed in 28-to-100-pin packages.
Microchip said the dsPIC-based devices are expected to be priced in a range of $3-to-$9 each in 10,000-unit quantities. Beta sampling of the first products is set for the fourth quarter 2001. General product sampling and hardware development tools are planned for first quarter 2002. Software development tools are planned for August. Microchip said it expects to move the first dsPIC products into volume production next year.