SAN JOSE -- Cypress Semiconductor Corp. here today announced a partnership with Munich startup MorethanIP GmbH to provide intellectual property (IP) and design cores for programmable physical layer devices (PHY) and complex programmable logic devices (CPLDs).
The IP and cores will support Cypress products for high-speed network infrastructure linecards. The IP and cores will be available as netlists or register transfer language (RTL) source code, and they will be optimized for both the Programmable Serial Interface series of programmable PHY devices and Delta39K CPLDs from Cypress.
Intellectual property and cores from two-year-old MorethanIP will enable Cypress to "provide comprehensive communications interface solutions for the rapidly-growing OC-48/STM-16 and OC-192/STM-64 data communications markets," said Chris Norris, vice president of the Data Communications Division at Cypress Semiconductor. The IP and cores are expected to help shorten development cycles for new broadband optical network systems, said the San Jose company.
The programmable approach to designs "allows integration of custom IP with the POS-PHY L3/Flexbus-4 IP/cores to enable standard communications interfaces to processors, framers and other chips on the board," said Deepak Sharma, senior IP and electronic design automation (EDA) marketing manager of Cypress's Data Communications Division.
The MorethanIP intellectual property and cores for PSI devices and Delta39K CPLDs will be available in the fourth quarter of 2001, with licenses starting at $12,000 for netlists and $18,000 for VHDL source code.