PALO ALTO, Calif. Sun Microsystems Inc. will build into its Ultrasparc processor both instruction-level and multithreaded parallelism, two of the most talked-about ways of coaxing additional performance from high-end 64-bit processors, EE Times has learned.
The move could pose a unique challenge to Intel Corp.'s IA-64 architecture and its Itanium processor, the first of the IA-64 devices. IA-64 makes heavy use of instruction-level parallelism, a technique akin to very long instruction word computing, but doesn't use multithreaded parallelism. Sun, for its part, has already developed multithreaded approaches for high-end workstations and servers, and it may be the first company to propose leveraging both techniques in one architecture.
"In the Ultrasparc 5 we have an architecture that can do both and allow the software environment to switch ahead of the workload," said David Yen, vice president and general manager of the processor products group at Sun Microsystems here. Sun, which recently announced a 900-MHz version of its Ultrasparc 3 processor, now has separate engineering teams working on the Ultrasparc 4 and 5.
Traditionally, Sun has relied on system-level performance and scalability to boost hardware performance. The company took the rare step of integrating a DRAM controller on its current Ultrasparc 3, enabling nonuniform-memory-based systems that can accommodate more than 1,000 processors.
It's also planning to introduce an external I/O scheme for its next spin of the Ultrasparc 3, due next year and based on 0.13-micron process technology. One possibility is Sun's recently described JBus, a cache-coherent chip-to-chip bus that can transfer data packets at speeds as high as 64 Gbytes/second.
But Sun's processors have generally lagged behind those of industry leaders such as Intel. "Sun's success is not driven by processor performance it's scalability," said Kevin Krewell, a senior analyst with MicroDesign Resources. "Backward compatibility is a big part of their pitch and value add."
Dipping into the latest bag of tricks for microprocessor design, the Ultrasparc 5 could provide a much-needed freshening up for the Ultrasparc line. Instruction-level and multithreaded parallelism are ways to keep a processor from becoming data-starved by hardware delays such as memory latency. In recent years, processor designers have warned that conventional performance boosters such as longer pipelines, deeper buffering and more speculation are running out of gas.
Sun, however, is trying to avoid leaning too heavily on instruction-level parallelism, which is the basis of the explicitly parallel-instruction computing (Epic) architecture Intel uses in its Itanium processors. Sun's Yen argued that Intel risks crippling IA-64 through an overdependence on immature compiler technology.
"Intel got obsessed pursuing that, and they have to rely on the compilers to identify all of the parallelism," he said. Placing so much faith in compiler technology, in Yen's view, "is a little bit of wishful thinking."
While there's a need for instruction-level parallelism in all modern MPUs, there's also a need to address "lightweight" processing jobs that don't need MPU performance so much as good sequential processing throughput. This is where multithreaded processing could be exploited, Yen said.
There are strengths and weaknesses to both approaches. Instruction-level parallelism is "static and has to be defined at compile time. When you compile something it could be in the L2 Level 2 cache or in main memory, and your compiler can't know that at run-time," said Krewell of MicroDesign Resources.
It's easier to tinker with instruction-level processing and optimize software compilers for it than it is to modify the hardware. Further, certain applications benefit if it has already been determined where the data is coming from, such as main memory or L2 cache, Krewell said.
Multithreading, by contrast, allows a processor to dynamically jump to other tasks when it encounters stalls from main memory, the L2 or hard disk. It's more akin to a multiprocessor system, except that the threads flow through a single device, Krewell said.
Yet multithreading can be a headache for software developers, as evidenced by the oft-cited problems of first-generation network processors based on this approach.
Sun has developed its own multithreaded architecture in its MAJC processor, and the company intends to ply that expertise in its Ultrasparc 5 device. "We learned a lot from that MAJC project," Yen said.
Yet Intel is no stranger to multithreading. Its own line of network processors exploits multithreading as a way to compensate for memory latency. And most recently, the company acquired the rights to the intellectual property of the Alpha EV8 from Compaq Computer Corp., a device expressly designed as a symmetrical multithreaded architecture.
But if Intel were to incorporate multithreading into its architecture, it would probably come after at least three more spins of the IA-64 that are already on the road map perhaps in 2004 or 2005, Krewell said.
Sun, for its part, is also hoping to get something out of Compaq's decision to sell its processor division to Intel by wooing former Alpha engineers to its processor design team in Boston. "We've been actively recruiting their ex-colleagues," said Yen.
Ultrasparc 5 will be the first real test of the multithreading technique on a general-purpose processor from Sun. Despite having its own instruction set with the potential for general-purpose processing, MAJC is being positioned as a graphics processor that will work in conjunction with Ultrasparc, according to Sun officials.
"We probably won't see the MAJC instruction-set ISA, but we'll see the spirit of MAJC in Sparc," Yen said.
The decision to relegate MAJC to a niche application reflects Sun's desire to stay focused on the Ultrasparc development. The company has some 1,200 designers in five design centers around the world working on Ultrasparc 4 and 5, and expects to add another 200 people by the end of 2003. About two-thirds of Sun's CAD development budget is dedicated to Ultrasparc, Yen said.
Moreover, Sun said it will continue to get first crack at Texas Instruments Inc.'s most-advanced process technology, as it has for the last 13 years. TI has some 200 engineers working with Sun to develop process technologies that will be competitive with Intel, IBM and Taiwan Semiconductor Manufacturing Co., said Dennis Buss, vice president of silicon technology development at TI.
The new process will rev the Ultrasparc 3 to 900 MHz and give it enough performance headroom to travel beyond a gigahertz. Yet even though Sun claims to have taken the lead in processors for workstations and servers, the speed grade is six months behind schedule, Krewell noted.
Currently, Sun is making the transition to TI's latest 0.15-micron process technology, which features a transistor gate width of 100 nanometers, seven levels of copper interconnect and an intermetal dielectric constant of 3.7. The Ultrasparc 4 will be based on TI's 0.13-micron process, while the Ultrasparc 5 will leverage 0.1-micron design rules.
Going forward, all new Ultrasparcs will use copper interconnect and migrate down to lower and lower k-value dielectrics. However, Ultrasparc will not use the performance-enhancing but controversial silicon-on-insulator process that both IBM and AMD intend to use in their high-end processors. Instead, it will stick to a traditional bulk CMOS process, a strategy similar to Intel's.