TOKYO Researchers at Hitachi Ltd.'s Central Research Laboratories (CRL) have created a sense amplifier circuit technology that they claim will allow the development of 1-volt multigigabit DRAMs.
The technology is being developed for Elpida Memory Inc., the DRAM venture of Hitachi and NEC Corp.
A 1-V requirement for multigigabit DRAMs built in sub-100-nanometer (0.10-micron) process technology using conventional sense amp schemes can lead to severe degradation of the amps' readout signal, slowing sensing speed below the 5 nanoseconds required for operation, said Riichiro Takemura at CRL's ULSI research department.
A key cause of the slower operation speed is the sense amps' shared common source line, which leads the sense amps to interfere with each other, said Takemura.
When a voltage is applied to the common source line, the first sense amp receives priority in the current flow, and the operation of the other sense amps is deferred.
To address this problem, CRL developed an overdrive scheme with distributed drivers and meshed power lines. That scheme, announced in February at the International Solid-State Circuits Conference, applies to 1-Gbit DRAMs operating at 1.4 V, but will not work with devices operating a 1.0 V, said Takemura.
Hitachi's new scheme allows current flowing through a single source node to flow to individual sense amplifiers, Takemura said.
The scheme adds one overdriver and one restore driver to PMOS nodes, and the NMOS nodes are connected to a sense driver. The technique frees the PMOS and NMOS source nodes from their neighbors, overcoming the interference and lowering the signal voltage, he said.
"In prior circuits, the sense amps disturb each other. With this new scheme, the disturbance is removed," Takemura said.
The prior overdrive scheme required a signal voltage of 130 mV, including a whopping 57 mV steering voltage to support an array voltage of 1.0 V. This signal voltage was above the 106 mV maximum voltage at which memory cells can work. The new layout cuts 47 percent or 27 mV out of the steering voltage, reducing it to 102 mV, he said.
"Achieving the 5 nanoseconds sensing time and 128 milliseconds retention time necessary for sense amps to work conventionally requires 130 mV signal voltage using the previous system. But 106 mV is the maximum voltage the memory cells can take. Our system provides just 4 mV margin, but before that there was no margin," Takemura said.
Takemura presented the scheme Wednesday (Sept. 26) at the International Conference on Solid-State Devices and Materials (SSDM) in Tokyo.
Adding the drivers and juggling the circuits should add about 13 percent to the sense amp area, but only about 2 percent in die area when applied to a 4-Gbit DRAM, said Takeshi Sakata, senior researcher at CRL's ULSI research department.
While the scheme works in simulation, Sakata declined comment on when Elpida might implement the technology and at what densities.
While aimed at the 4-Gbit density, the technology can be applied to DRAMs down to the 512 Mbit density, Takemura told EE Times.