SANTA CLARA, Calif.--Integrated Device Technology Inc. here has integrated high-speed queuing logic and first-in, first-out memory to offer a new series of multi-queue FIFOs for fast networking applications, such as terabit routers, multi-service switching platforms, and wireless base stations.
The new high-speed queuing FIFOs are able to handle sustained throughput rates up to 7.2 gigabits per second, said IDT. The series also offers a range of configurations with FIFO desntieis of up to 2 megabits.
"The multi-queue family addresses a long-standing need for an off-the-shelf approach that can assist with the queuing and scheduling design issues of these high-performance applications," said Mario Montana, director of IDT's FIFO division. "The multi-queue architecture provides a fast, space-efficient hardware-assist block to our customers who are attempting to differentiate themselves with improved bandwidth and QoS quality of service features."
IDT said the FIFO architecture offers between one and 32 discrete queues that may be configured on the device at initialization. Individual queue sizes and full/empty flag boundaries are user-programmable, allowing system designers to differentiate the priority of data traffic. If higher queuing densities are required, the devices may be cascaded to implement up to 256 prioritization queues, thus allowing for scalability, said the company.
By offering speeds up to 200 MHz in by-36-bit configurations, the multi-queuing FIFOs support line-speed performance equivalent to three OC-48 flows in one device. IDT's multi-queue family also offers bus-width matching capabilities, allowing each port to be configured at by-9, -18 and -36 widths.
Samples of the 3.3-V devices are now available with production deliveries starting soon. IDT plans to make available 2.5-V versions in the first quarter of 2002. Multi-queue FIFO devices are housed 256-ball BGA packagies and start at a price of $35 each in quantities of 10,000.