TOKYO -- Toshiba Corp. today claimed to be the first to introduce a 64-megabit pseudo-SRAM series, which is aimed at memory applications in next-generation wireless and portable systems.
The new PSRAM memories are fabricated with 0.175-micron design rules and packaged in 48-ball fine-pitch ball grid-arrays. The memories are both configured 4-Mbit-by-16 and support 80- or 85-nanosecond access times.
Toshiba said the pseudo-SRAM devices are designed to bridge the gap between conventional SRAMs and DRAM memories--containing the most desirable features of both types of memory architectures. These memories are based on a high-density one-transistor DRAM-like cell, while providing SRAM interfaces.
"Toshiba's 64-Mbit PSRAM meets the high-density memory requirements traditionally satisfied using a DRAM solution, while providing the design flexibility and low power essential for wireless and portable applications," said Paul Liu, manager of business development for SRAMs at Toshiba's U.S.-based subsidiary in Irvine, Calif. He said the increase in portable applications was driving designs to new features that require greater amounts of storage.
The new 64-Mbit series supports two clock configures. One has address input pins latched by the falling edge in each read/write cycle. Another new clock scheme has input pins latched by falling edges of two pins--one in the read cycle and the other in the write cycle--for more of a "seamless SRAM-like" operation."
Samples of Toshiba's 64-Mbit PSRAM will be available in October, priced at $42 each. Full production is scheduled to begin in January 2002.