BALTIMORE Chip makers will be forced to "test smarter" with new, adaptive testing methods in order to maintain historic quality levels without increasing costs, according to Phil Nigh, a senior engineer at IBM Microelectronics, speaking Tuesday (Oct. 30) at the International Test Conference.
"Product test methodologies must be defined through a partnership among product design, technology development and test engineering to optimize the trade-offs among product quality, design-for-test and manufacturing costs," said Nigh, who develops test methods for next-generation ICs. "In many cases, this partnership will cross company boundaries."
Revolutionary advances such as 300-mm wafers, copper interconnects, silicon-on-insulator technology and systems-on-a-chip are being introduced to production at a breakneck pace that challenges existing capabilities in order to meet the market place's insatiable, accelerating appetite for newer, faster, better products, Nigh said. "Test is the final arbiter the gatekeeper of time-to-market, design verification, and manufacturing," he said.
As test and reliability screening methods such as IDDQ and burn-in lose effectiveness for devices produced in technologies finer than 0.15 micron, new materials such as SOI, features such as 1-GHz clocks and chips with more than 100 million transistors require improved screening methods, Nigh said. Methods intended to identify die anomalies that don't meet acceptable norms will find greater use, he said. "The use of cheap DFT design-for-test testers has changed from a 'wish list' item to an absolute requirement for many products."
The introduction of 300-mm wafers will lower the cost of production per die, but test costs measured as a percentage of product cost will increase if test costs remain constant, Nigh warned. At the same time, historic cost-reduction methods such as highly parallel testing for DRAMs and burn-in avoidance for ASICs are being challenged.
But the most profound affect on IC testing may be the shift by suppliers from the integrated device manufacturer model to the fabless business model.
Fabless companies face major issues in developing tests and reliability screens when they have little knowledge of defects that occur on wafers produced by a foundry.
The evolution of the IC industry may see a chip's design to-test flow pass from company to company, Nigh said. Citing an example of a chip traveling through eight different companies for library development, IP development, design, test development, wafer fabrication, packaging, test and burn-in Nigh asked: "How do you take charge of the problem over eight companies?"
Partnerships among EDA, test and design houses could counteract the threat of losing control of the problem, he said.
An understanding of the relative effectiveness of various test methods is critical, Nigh said. The importance of DFT in enabling these methods will require that manufacturing test methods be defined by a product design team before any hardware is built, and many times before the technology is fully developed.
"But how can the design team ensure that the tests are effective if they have little information about the manufacturing defects that occur in the fab?" asked Nigh.
New test methods are needed, including alternative approaches to defect-oriented testing, he said. "Given the need to improve technology development times, improved methods of fault diagnosis and process characterization must be developed," Nigh said.