GENEVA -- STMicroelectronics today described the first very-long instruction word (VLIW) microprocessor core resulting from an ongoing partnership with Hewlett-Packard Co. that began in 1998. The scaleable, customizable core has been designed for embedded use in multimedia system-on-chip (SoC) designs, with the ability to execute up to four instructions per clock cycle, said the company.
By executing four instructions per cycle, the ST210 core is capable of delivering 1-GHz performance while maintaining power consumption levels of a 250-MHz clock frequency, said the European chip maker. The VLIW processor core is primarily being aimed at video/audio streaming applications, such as MPEG-2, MPEG-4 and MP3 in digital consumer systems.
ST and HP designers are working on high-performance processor cores and development tools that enable developers to accelerate the creation of scaled and customized SoC chips for specific applications. The collaboration involves a central design team, based in Cambridge, Mass., and other engineering groups in the England, Italy, France, and California.
The ongoing development project aims to leverage HP's knowledge of compiler technology with ST's know-how in system-on-chip designs to "offer OEMs a unique, new option in terms of speed, power, cost and time-to-market," said Andrea Cuomo, vice president of the Advanced Systems Technologies Group at STMicroelectronics. "The ST210 demonstrates not only the fundamental correctness of our approach but also its commercial viability," he stated.
Samples of a test chip, called the ST200-STB1, are scheduled to be out by the end of November to provide customers with a demonstration vehicle for future applications.
STMicroelectronics claimed that the ST210 core outperforms all existing dedicated multimedia processors and VLIW cores in terms of architectural simplicity and silicon area, effective processor speed, scalability and customizability. Many functions are implemented as software algorithms instead of hardware circuitry, which makes customizing the VLIW-based device easier, according to the two companies.
According to ST, any possible variation of the processor's machine model can be exposed to an unchanging compiler, which schedules code to optimally suit the new machine by way of advanced algorithms that extract "Instruction Level Parallelism" (ILP) inside applications written in C. This optimization results in highly efficient usage of the underlying hardware architecture, said the company. The approach translates the architecture directly into a smaller number of functional units, resulting in a smaller chip area and reduced silicon costs compared to other VLIW machines available on the market, said ST.
"We are already exploiting these advances in new SoC designs for audio decoding and MPEG video encoding in applications such as DVD players and recordable DVD," said Philippe Geyres, corporate vice president and general manager of the Consumer & Microcontroller Groups at STMicroelectronics.