MOUNTAIN VIEW, Calif.--Synopsys Inc. today announced it has agreed to acquire technology assets from nearby C Level Design Inc., and it will integrate the company's CycleC simulation tool into its VCS simulator to accelerate HDL simulations.
Synopsys said it also is buying technology behind C Level Design's System Compiler software for RTL-C synthesis as well as a patent for synthesizing high-level languages into HDL.
The Mountain View design automation giant said the transaction will not include any products, service businesses, customer agreements, or other assets and liabilities of C Level Design. Campbell, Calif.-based C Level Design will discontinue sale and support of all products and services. Terms of the transaction were not released.
Synopsys said the CycleC simulation technology will complement its recently introduced DirectC interface within in the VCS simulator. This will provide customers with faster cycle-accurate simulation performance when using a mixture of Verilog and C++ languages, said the company.
"The addition of the CycleC technology will benefit customers by making it easier to accelerate their VCS simulations using cycle-accurate C and C++," said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys.