WILSONVILLE, Ore. -- Three months after disclosing an ambitious plan to redefine design software for field programmable gate arrays, Mentor Graphics Corp. here is preparing to ship its first beta versions of knowledge-based, heuristic synthesis tools targeted at next-generation FPGAs with up to 50 million "ASIC gates" on a chip.
"From everything we are now seeing, the industry should be at about 50 million gates up from 4-to-6 million today around the 2004-to-late 2005 timeframe," said Michael Bohm, chief scientist for Mentor's recently created FPGA Synthesis Group. "That size in capacity messes up software databases and everything else, across the board. It breaks timing engines and other aspects of tools, and forces you to take hierarchical approaches vs. what had been a flat approach to designs," he told SBN in a recent interview.
Mentor launched the FPGA Synthesis Group in the summer to pool resources from across the company to execute a new programmable logic synthesis technology roadmap, dubbed "Project Atlanta" (see Aug. 6 story). The roadmap aims to deliver new FPGA design synthesis tools in three phases between now and early 2004.
"FPGAs are moving a lot faster than I would have ever expected," said Bohm, referring to increases in gate densities and chip-speed performance due to leading-edge technologies now being applied to programmable logic. "What took ASICs about 15 years to cover, we're seeing FPGA technology advancing in just five. That's much quicker than anyone expected."
The acceleration in FPGA chip technologies is a direct result of programmable logic suppliers having access to leading-edge processes at silicon foundries. The world's two largest pure-play foundries--Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and United Microelectronics Corp. (UMC)--both partner with FPGA suppliers to use high-density programmable logic as process-learning curve vehicles, much like DRAMs were used in the 1980s and early 1990s.
"FPGAs are basically RAMs. The lookup table is a 16-by-1 RAM, and they are completely testable," Bohm noted.
With high-density FPGAs now available, system designers are turning to programmable logic for even high-volume consumer products, such as MP3 players and video cameras, partly because of shrinking lifecycles of systems. And that trend is adding pressure on design tools suppliers to redefine synthesis technology for FPGAs instead of applying more traditional ASIC-based concepts, according to Mentor, which gets about 25% of its revenues from software used on programmable logic.
The first phasein the "Atlanta" project--now set to ship beta tools to selected customers in November--is focused on heuristic synthesis, which bundles design knowledge into software for generation of complex structures in specific FPGA chip architectures. Mentor has dedicated groups of engineers to work on heuristic synthesis engines for each major FPGA family from Xilinx, Altera, Lattice, Agere and others.
"When you build a counter in one of these technologies, it is built differently for each FPGA series," Bohm said. Mentor calls these heuristic synthesis engineers "designers/software programmers" because "they know a little bit of both worlds," said the chief scientist.
The new heuristic synthesis tools are being set up to handle 50 million gates with a lot of embedded encryption methodology to protection of customer intellectual property (IP). The heuristic synthesis tools will also pack a new timing engine that completely edge based for multiple clock domains and complex timing analysis, Bohm said. And the new heuristic tools will contain a lot of core technology from Exemplar Logic, a design synthesis pioneer owned by Mentor.
The first new heuristic synthesis tools are slated to become generally available by the first quarter of 2001. After that phase, Mentor aims to roll out a new breed of FPGA-oriented physical synthesis tools, which will enable designers to optimize placement of functions on a programmable logic device. These physical synthesis tools will be out sometime in the middle of 2002, according to the Project Atlanta roadmap.
"Timing closure has become a big issue in FPGAs just like it has been in ASICs," Bohm explained.
The physical synthesis tool will hunt for the best location of functions to improve performance. "This is completely different that with ASIC design. For example, we have a ton of extra flip-flops sitting around in combinational elements all over the die," Bohm said.
"By putting a function in the right place on the die--replicating and putting down in a certain area--you can make paths much quicker. We are expecting to see anywhere from 30-to-40% improvements in chip speeds by using physical synthesis," Bohm said.
The final phase of Mentor's Project Atlanta roadmap targets high-level synthesis for FPGAs to help engineers examine tradeoffs in design, such as implementing a function in software or hardware. The high-level synthesis tools are expected to be available by early 2003. These synthesis tools will accelerate product development by speeding simulation of early design concepts by 10,000 times since they will be run at an abstract level, according to Bohm.
"We will be able to synthesize C code software into hardware, and run the hardware function right next to an embedded processor inside an FPGA," said Bohm, in providing an example of how the high-level synthesis tool will be used. "We see a lot of advantages in FPGAs vs. standard ASICs. Once an ASIC chip is built, you can not leverage the tradeoffs of hardware and software."
"We believe synthesis is the lynchpin for FPGAs, just like the other chip design segments in the past two decades," said the chief scientist. "This will open up product development to the 'garage shops' again that have found it more difficult to work with complex system-on-chip designs in the ASIC world," he predicted. "I expect to see a lot more innovation, new startups, and design concepts that were blocked by high costs."