COLORADO SPRINGS, Colo.--Ramtron International Corp.'s Enhanced Memory Systems Inc. subsidiary here and Singapore's United Test and Assembly Center Ltd. today announced development of a new chip-scale package, using flip-chip technology, for a 72-megabit double data rate static RAM.
The high-pin count package employs wafer-bump interconnects and flip-chip technology for higher electrical and thermal performance compared to other IC assembly techniques, said Enhanced Memory. The flip-chip, chip-scale package, called FC CSP, will be used on the recently introduced 72-Mbit DDR Enhanced SRAM, developed by the Ramtron subsidiary.
Enhanced Memory's 72-Mbit DDR ESRAM is targeted at workstations, servers and high-performance communication systems.
The FC CSP package was developed by three-year-old United Test and Assembly Center (UTAC) for high-pin count, small form factor IC applications. The new packaging technology uses established flip-chip packaging processes, according to the Singapore-based chip assembler and test supplier. The addition of wafer bumping allows the entire surface of the IC to be used for interconnects in the package, improving the performance by lowering signal interference and cross talk, said the company.
UTAC is expanding its flip-chip assembly capability to serve a range of applications, from high-speed routers and workstations to wireless handsets, said Albert Ng, vice president, sales and marketing, of the company. The company said its flip-chip process accommodates bump pitches of 200 microns for peripheral bumps and 250 microns for array bumps. The company said all FC CSP packages are qualified to Jedec's MSL 3 requirements.