SAN JOSE -- Circuit Semantics Inc. today announced new features and an option to its IC-design timing and characterization software, which are aimed at allowing users to customize tools by an application program interface.
The San Jose company said the new release will significantly increase the accuracy, performance, and automation of design and timing analysis tools by allowing users to manipulate and access the data. With the API interfaces, users can customize the tools and integrate them more tightly into design and verification flows, said Circuit Semantics.
The new release of DynaCore, DynaCell, and DynaModel and the new DynaTest option offer full support for Berkeley Spice BSIM4.2 models, in addition to the BerkeleyBSIM3 models currently supported by the system.
"With the ever-increasing scale of designs, design engineers need high-performance, customizable tools that can manipulate all design data," said Gary Larsen, president and CEO of Circuit Semantics. "This major upgrade of our core technology has made it easier for our customers to access characterization, analysis and timing data to meet their specific requirements. This improves individual flows that results in a further reduction in design cycle times."
A key enhancement to DynaCore is an incremental option that utilizes a persistent database, said the company. The incremental option will dramatically reduce engineering change order (ECO) turnaround time, according to DynaCore.
Enhancements to DynaCell include the ability to characterize multiple voltage I/O pads and the capability to automatically validate the models written out by the tool and automatic generation of vital views. Power characterization now includes state dependent leakage power and "hidden" or "quiet power" characterization, which now give designers a comprehensive solution for power analysis, said Circuit Semantics.
The new DynaTest option to DynaModel allows users to write out Verilog ATPG gate-level models of the full custom transistor-level design. Circuit Semantics said DynaTest is the first tool to achieve dramatic reductions in the time required to model custom transistor-level design for ATPG tools.