SAN JOSE -- LogicVision Inc. here has struck a couple of design-automation partnerships to expand the use of embedded test technology, including an agreement with Atrenta Inc. to enable validation of test requirements early in IC development.
LogicVision today said it has selected San Jose-based Atrenta as a strategic partner in making embedded test verifiable in the RTL stage of chip design vs. later when ICs are physically laid out. By checking the register transfer level (RTL) code, LogicVision and Atrenta said it will be possible to save weeks or even months from a development project by eliminating rework of chip designs when rules were violated.
"Partnering with Atrenta is critical in providing our customers with a capability to improve the predictability of embedded test insertion at the beginning of the design phase, helping to shorten electronic product development cycles," said Vinod K. Agarwal, president and CEO of LogicVision. "The RTL rules sign-off is a necessary pre-requisite to any viable RTL-to-GDSII flow." The GDSII format is used to describe the physical structure of an IC design for photomask tooling.
LogicVision and Atrenta said they will work together to develop sophisticated rules designed to catch complex problems responsible for bus contention, clocking violations, and undesirable state changes in chips. By solving these kinds of problems at the RT-level, designers will be another step closer to having sign-off quality RTL code, said the two companies.
"By working together, we will enable ASIC and SoC system-on-chip designers to develop RTL that is fully compliant with LogicVision's embedded test flow and automation software, significantly reducing the time required for subsequent embedded test implementation," said Ajoy Bose, chairman, president and CEO of Atrenta. "This will help bridge the gap between design engineers and test engineers."
Six months ago, Atrenta introduced its SpyGlass rule checker software, which uses a look-ahead engine to predict and analyze potential conflicts between IC designs and manufacturing processes (see June 5 story).
In a separate agreement, LogicVision this week said it would collaborate with MoSys Inc. in nearby Sunnyvale to qualify and deliver embedded test and built-in repair analysis capability for the MoSys's 1T-SRAM embedded memory. The two companies said they have already verified the integration and implementation of LogicVision's Memory BIST and top-level test assembly technologies on the 1T-SRAM embedded memories.
"The embedded test and analysis functions provided by LogicVision combined with a built-in repair analysis capability streamline the testing and built-in analysis of the memory for redundancy repair," said Mark-Eric Jones, vice president and general manager of intellectual property at MoSys.
Availability of the full-embedded test and built-in repair analysis solution is scheduled to be released by the end of this year.