TOKYO A technology with the improbable name of silicon-on-nothing (SON) could emerge as a candidate to replace silicon-on-insulator (SOI) as a technique for improving logic circuit performance given Toshiba Corp.'s successful construction and testing of a SON MOSFET, the company's engineers said.
Toshiba's advanced ULSI engineering team has made a SON MOSFET with a 0.14-micron gate length and a junction capacitance 20 percent lower than a transistor manufactured in bulk silicon. If the bubble-like void carved under the gate of the MOSFET substrate can be made bigger it now takes up 20 percent of the substrate area under the gate the technique could double the performance boost available with SOI, but at a fraction of the cost, said Yoshitaka Tsunashima, group manager at the advanced ULSI process engineering department of Toshiba.
Toshiba is showcasing the SON technology this week at the International Electron Devices Meeting (IEDM) in Washington.
"We believe this is the next step beyond SOI," Tsunashima told EE Times.
SON, has several advantages over SOI in terms of manufacturability and performance, Tsunashima said.
SON technology builds on work described by Tsunashima at IEDM in 1999, called Empty Space in Silicon (ESS), which cut a slice through a silicon substrate to form a dielectric. But unlike SOI, the ESS technique didn't need ion implementation and high-temperature annealing. If a pattern of voids could be carved under transistor gates, Tsunashima believed the technique could radically cut parasitic resistance and boost performance speeds.
"Everyone at IEDM '99 was wondering if we could apply ESS to make transistors, and we wondered too, until this summer when we fabricated our first SON MOSFET," Tsunashima said.
Unlike SOI, the SON technique requires an uncomplicated manufacturing process that should be 75 percent cheaper than the Somox SOI process, for example, Tsunashima said.
Furthermore, while SOI can reduce junction capacitance 45 percent compared to bulk silicon, SON could bring this down to 25 percent of bulk silicon, according to Tsunashima.
Toshiba also believes SON will aid its heavy investment in trench-based embedded DRAM process technology by allowing the company to boost the performance of its logic circuits while keeping embedded DRAMs on the same chip.
"There is no limitation on the layout," said Tsunashima. "Unlike SOI, we can put SON wherever we like on the wafer. It means we can keep the benefit of SON and keep our embedded DRAM. This will prove very useful for our future SoC chips."
Toshiba is not alone in investigating alternatives to SOI, as other companies are also embedding dielectrics into substrates. STMicroelectronics has been working with France Telecom to develop its own version of SON, using an epitaxial process to bury a 5- to 20-nm silicon film channel under the gate stack. This "super SOI" process requires silicon germanium, silicon epitaxy and additional process steps, although STMicroelectronics points out that none of the steps require new equipment, materials or techniques.
Tsunashima said he is now awaiting test results on a thinner SON MOSFET with a 0.12-micron gate length.
While Toshiba has yet to make a functioning chip using SON, the company is confident it can apply the technology to its 50 nanometer (0.05-micron) process generation around 2005, according to Tsutomo Sato, a research engineer at the process and manufacturing center of Toshiba's advanced ULSI process engineering department.
"We plan to implement this technique in 2005 for the 35-nm gate length generation," Sato said. "Other companies can make SOI for this generation, it's just a kind of know-how. But there is no problem, we feel, with scaling SON, it's such a simple process."
Meanwhile, Toshiba has taken over 20 patents on the process and will be pushing the technology into test circuits over the next six months, Tsunashima said.
"The next step is to make circuits," he said. "We want to demonstrate this at next year's IEDM."
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