TOKYO ( ChipWire) -- NEC Corp. will begin taking orders this spring for cell-based designs to be built in the company's most advanced 0.13-micron (drawn) process technology, and aimed at low-power and mobile devices.
NEC will roll out the library in phases throughout the year starting with low-power devices and concluding with high-performance, copper-based designs.
The 0.13-micron CB-12 library is divided into four categories. The "L" library is for devices requiring the lowest power consumption and extended stand-by times. Clock speeds for this library max out at 100 MHz.
"M" is the mid-range library, offering power-management features and frequencies between 100 and 250 MHz. The "HM" library offers speeds up to 450 MHz. Beyond that is the "H" library for cores -- such as microprocessors -- that will run faster than 450 MHz using copper interconnect.
NEC will start taking orders for the L and M libraries in April, provide first samples in June and begin volume production in August. HM library orders will start in June, while the high-performance H library will be available at the end of the year.
Based on NEC's 0.13-micron drawn and 0.10-micron UX4 process technology, CB-12 chip designs will have the highest level of performance, lowest power consumption and density the company has to offer for cell-based designs. Using the HM library, for example, logic gate delay time is measured at 11.1 ps at 1.5 V, modeled for an inverter with a fanout of two, and 15.9 ps for a two-input NAND gate with a fanout of two.
NEC also cut its logic power consumption in half, so that a logic gate now consumes 7.3 nanowatts per MHz. For the L and M libraries, up to 32 million logic gates can be integrated in one design. Customers can mix and match logic cell libraries according to their power and performance needs.
For on-chip memory, NEC is offering two SRAM macros, a six-transistor cell -- which is common in compiled-type memory -- and a loadless four-transistor SRAM cell for high density. One- and two-port memory is available for the compiled SRAM, and one port is offered for the four-transistor type. FIFO, CAM, ROM, DRAM and flash memories are being offered as common intellectual property.
NEC's core lineup spans the breadth of consumer, mobile, PC, graphics and networking applications. Available processor cores include the 32-bit V850E, the 64-bit VRx series and an MPEG-2 encoder/decoder. For mobile communications, the company is offering a DSP and modem codec, and for wired communications it has ATM, Ethernet, ADSL and VDSL. The company will also provide a 2-D/3-D accelerator, NTSC/PAL encoder, PCI, USB, Direct Rambus, UART, A/D, D/A, IEEE1394 and digital and analog PLLs.
While the internal power supply is 1.5 V, full-swing I/O buffers for 2.5- and 3.3-V interfaces can be applied. Available I/O blocks are LVCMOS/LVTTL, a low-noise through-rate buffer, a three-state buffer and an open drain buffer. High-speed interfaces offered are the Intel-compatible GTL+1, HSTL, pECL, SSTL, LVDS, AGP, PCI, USB and IEEE1394.
Customers will be able to choose from an assortment of packages, including flip-chip, chip-sized and standard. Chip scale can accommodate up to 600 pins, while flip-chip can hold as many as 3,000.