SAN JOSE--Cypress Semiconductor Corp. here today launched its radio-frequency chip business with the introduction of RF phase-lock loop products supporting 0.5- to 2.5-gigahertz frequency outputs. The new series of PLL devices is aimed at broadband networks, RF base stations, wireless local loops, cellular phones, and cordless telephone handsets.
Cypress said it has been serving wireless applications with low-power SRAMs and spread-spectrum frequency timing generators, but the new RF products will diversify its portfolio for mobile communications systems. According to the San Jose company, the family of radio-frequency PLLs features the industry's lowest phase noise floor for clearer voice and higher throughput in digital data transmissions.
"Our RF family of devices will enable us to penetrate further into the market for cell phones and handsets, and to gain a beachhead in base stations, wireless infrastructure, and other wireless markets," said Dan McCranie, executive vice president of sales and marketing at Cypress.
Cypress said it gained access to RF technology through last year's acquisition of IC Works, a Silicon Valley supplier frequency timing generators (see Jan. 21, 1999, story). IC Works was combined with Cypress's Timing Technology Division.
Cypress CEO T.J. Rodgers likes the volume potential of wireless products. "All the signs point toward a wireless world with ubiquitous computing and multiple handheld devices," Rodgers said. "There are three cell phones shipped for every PC. This RF chip is our third entry into that arena, along with our Premis clocks and ultra-low-power MoBL SRAMs."
The company's CYW23xx family consists of three single-PLL and six dual-PLL devices. Cypress claimed that the devices offer the industry's lowest-phase-noise-floor while maintaining footprint and register compatibility with LMX23xx series of National Semiconductor Corp.'s PLLatinum phase-lock loop chips. The company said recent tests shows its CYW2336 has 3 dB lower noise than National Semiconductor's LMX2336.
Cypress' products are fabricated with 0.65-micron technology. The company said it aims to port the RF chips to its 3.3-volt, double-layer-metal, 0.25-micron BiCMOS process, which is expected to maximize RF integration and bring an optimal mix of speed, power, and cost to wireless applications, said Cypress.
The BiCMOS technology is will produce reusable analog/mixed-signal intellectual-property (IP) blocks, which are expected to be used in other RF and high-speed physical-layer devices, according to Cypress. The new process is compatible with an existing 0.25-micron SRAM technology, and it is expected to make it easier for designers to mix and match IP in future products, Cypress said.
The CYW23xx family is available now in 20-pin TSSOP packages, and priced in a range of $2 to $3.50 each.