"Red brick wall" probably won't faze chip makers, says TI's Doering

BURLINGTON, Mass. -- Fears of hitting a "red brick wall" in semiconductor technology in the next 10 to 15 years don't appear to be stopping semiconductor makers' headlong rush to meet it, said Robert Doering, senior fellow in silicon technology development at Texas Instruments Inc., addressing a SEMI New England breakfast forum here Wednesday.

While it always remains possible the industry will find innovative ways to overcome those obstacles, he said, the industry has also always counted on pushing the wall a little further back. At this point it seems to remain implacable, at least for now.

"The brick wall has held steady for the last few roadmaps," Doering said. "It's not a wall on wheels."

When the Semiconductor Industry Association released the 1999 International Technology Roadmap for Semiconductors last fall, it included a list of technical hurdles -- called the "red brick wall" -- that it expected to hit in the next decade and a half. Some of those include pushing DRAM half-pitch below 180 nm by 2002, reducing MPU gate lengths to 65 nm by 2005, and developing inter-metal dielectrics with k constants as low as 1.6 by 2005.

Most appear reachable, said Doering, although "there are questions about which solution will work" or if the time frame for finding solutions can stay on track.

Then there is a red area where there is no consensus on solutions, he said, where the industry needs real breakthroughs.

This has happened before, such as when the industry developed deep ultraviolet lithography, step-and-repeat on-wafer patterning, and the MOS transistor, Doering pointed out.

Perhaps the most formidable barrier is to finding a successor dielectric interconnect material to the venerable silicon dioxide, which "is nearing the end of its life," said Doering. "If we are to continue to reach the new smaller gate lengths of future generation nodes, we must find a new dielectric material."

Current silicon dioxide dieletric material must now be no more than four or five atoms thick in order to give the high performance needed in leading-edge chips. According to TI's Doering, the chip industry has about reached the physical limit of how thin silicon dioxide lines can be made.

Doering believed that in the near term -- for the next three to four years -- silicon nitride can become a new dielectric for high-performance chip interconnect. "In the longer term, of the next 5 to 10 years, even more revolutionary materials will be needed," he said.

Two classes of new materials for the long term are under study: metal oxides and metal silicates. He listed titanium oxide as a promising dielectric. The metal silicates add oxygen to metals such as titanium or zirconium. He said some researchers are looking at ferroelectric materials for very dense interconnect lines. This includes some of the materials, such as BST (barium strontium titanate) that is also being considered by DRAM makers for very dense capacitors.

The TI researcher said, "Chemistry is marvelous and they always come up with a way" to leap a technical hurdle. But he indicated that the average time it takes for a breakthrough technology or tool to go from development to production is six years. "So you have to start early," he said. According to the SIA roadmap, the red brick wall for dielectrics, junction depths and oxide replacements is positioned right about 2006.

"The hope is that it will recede. There's not evidence of that yet," Doering said.

He said it was likely that chip makers would simply rush to the limit. "They probably will push as fast as possible rather than maximizing the profit from each node," the TI researcher said. "Competition is fierce and people will try to get there as fast as they can."

And the hoped-for breakthroughs may well materialize, given past experience, he said. But then the question will be whether the new technologies could be too expensive to be cost effective.