SUNNYVALE, Calif.--The Knights Technology a division of Electroglas Inc. today announced development of a software tool for Infineon Technologies AG that automatically checks for design-rule violations while chip engineers layout the locations of bond wires between the die and package leadframes.
Knights' post-layout bond tool assesses the fit of each bond wire with respect to the geometric constraints of the package. The software generates wire-bond diagrams and provides coordinates for wire bonder equipment used in chip assembly plants.
Infineon and other chip makers have built large libraries of package CAD data and design rules. One problem with proprietary rules is that they might not be easily transferred to commercial rule-checking programs for bond-wire placement. When done manually, the task of verifying the placement of each bond wire between a die and leadframe can take a long time, and errors can occur, said Knights.
Experience with GDS II data, graphics and geometric calculations enabled the Electroglas division to create a post-layout bond tool for Infineon, said Michael Brugel, product specialist at Knights. "The tool is a prime example of the application support we offer from the service side of our company. In this case, our engineering team in India developed the software, in less than three months," he said.
The task of verifying bond-wire placement is growing. "Over time, we had developed our own library of over five hundred different packages," noted Werner Schiele, CAD manager for Munich-based Infineon. "As the number and different types of checks had increased, we needed to automate the bond generation and verification process."
Knights' post-layout bond software was develop in Java and has been configured to run on Sun Microsystems' Solaris workstations and personal computer platforms. Knights said the tool checks for shorted wires, wires incorrectly placed, checks the angle between wires, length of a wire, distance from the edge of a chip to the package and many other rule constraints.