SAN JOSE--Mentor Graphics Corp. and Mips Technologies Inc. today announced a jointly-developed environment for pre-to-post silicon development. The development and debug environment is aimed at system-on-chip designers using Mips' 32-bit processor cores. It provides designers with a single graphical user interface to Mentor's Xray Debugger.
The environment is intended to accelerate the introductions of SoC designs with 32-bit RISC cores in networking, communications, digital consumer, and portable systems applications. Mentor claimed the integrated environment is the first to provide pre-to-post silicon support for SoC development projects.
"From industry standard co-verification tools to post-silicon debugging, Mentor is the first and only company to offer a comprehensive, integrated environment for the end-to-end development and debug of SoCs," declared Brian Knowles, vice president of marketing for Mips Technologies.
Mentor said its Xray Debugger enables testing and prototyping of applications software when used with the Mips32 Instruction Set Model (ISM). This engineering work can be performed before hardware is available or while hardware design is still underway, according to Mentor. Once the hardware design is underway, the Xray Debugger works in combination with Mentor's Seamless co-Verification Environment to check the integration of hardware and software for errors that often go undiscovered until the first ICs are fabricated.
The Xray system also supports software debug on prototypes and final hardware. An Enhanced JTAG interface (eJTAG) connects Mentor's Xray Debugger to host targets.
Mentor said it is making the development tools available for the MIPS32 series of processor cores on Sun Solaris workstations, Windows 98/NT platforms, and other hosts.