SAN JOSE -- Altera Corp. here today announced the latest version of its Quartus development software, which features enhanced timing-driven compilation algorithms and an improved internal timing estimator. Altera claimed that, on average, these improvements can increase design performance for high-density APEX 20K and APEX 20KE programmable logic devices by 40%.
Altera's Quartus version 2000.02 release also allows designers to set I/O timing constraints to optimize total system performance. With the new timing-driven compilation capability, designers may separately optimize timing for the I/O pins and the internal (core) logic. Setting timingconstraints for I/O pins allows the Quartus software to compile for optimum I/O timing, thus enhancing overall system performance. For optimizing internal (core) timing, this version now features an extra0effort mode.
Altera said switching to this new algorithm improves design performance by over 40% on the flagship EP20K400E device.
"Design performance and system bandwidth are critical factors for our customers today," said David Greenfield, Altera's director of development tools marketing. "This latest Quartus release delivers a dramatic performance boost that will have an immediate positive impact on APEX
Altera developed the Quartus software to support system-level designs and features good as native links to third-party tools from Exemplar Logic, Model Technology, Synopsys, Synplicity, Viewlogic, among other EDA vendors. It also features an embedded logic-analysis tool for in-system hardware debugging.
The Quartus version 2000.02 design software will be available to customers this month. It is also part of the Altera development tools subscription package, which costs $2,000 for a single-user license which entitles a customer to receive the latest version of MAX+PLUS II and Quartus development tools, as well as all software updates for 12 months.