HSINCHU, Taiwan -- Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. here today rolled out its 0.15-micron process generation, disclosing plans to offer three different versions of that technology node for low-voltage, high-density, and low-power dissipation chip designs.
TSMC is also offering three interconnect options with aluminum, copper, and a combination of those two metals in the 0.15-micron (drawn-feature size) process. The foundry company plans to ramp 0.15-micron production two 8-inch wafer fabs this year, adding to two more factories by the end of 2001. Early customers are expected to be qualified for 0.15-micron production by June.
In April, TSMC said it plans to ship its first all-copper interconnect ICs with the 0.15-micron technology to development partner Altera Corp. of San Jose. TSMC used Altera's 400,000-gate programmable logic device as the production-test vehicle for the initial all-aluminum 0.15-micron process. The same six-level interconnect device will be used again to prove out 0.15-micron copper processes.
The Altera test chip is a shrunk version of an existing 0.18-micron IC, which is being produced by TSMC. According to the Taiwan foundry company, the 0.15-micron aluminum process reduced the die size of the design by 26% and improved performance by 25-30% over the existing 0.18-micron product. Four lots of 8-inch wafers--totaling of 96 substrates--have demonstrated yields similar to 0.18-micron processes, according to Sheldon Wu, senior director of field technical support for North America based in San Jose.
TSMC said 0.15-micron production will accelerate into high volumes in the third quarter of 2000. Initially, volume production will start with TSMC's low-voltage (1.2-V core voltages) and base-line (1.5-V core) 0.15-micron process. The 1.2-V version of the process will have an effective gate length of 0.11 micron and gate delays of 19 picoseconds. This version will be targeted at low-voltage, high-performance applications, including microprocessors, graphics chips, networking ICs and high-speed SRAMs. A special option will also be available for central processors with 14-ps gate delays, said TSMC.
The base-line 0.15-micron process for high-density IC applications will also be available in the initial offering. This is a shrunk version of TSMC's low-voltage 0.18-micron process, capable of system-on-chip integration for computing and communications SoCs, and high-density programmable logic. It has an l-effective gate length of 0.13 micron.
About three months after the initial 0.15-micron processes become available, TSMC will offer a new low-power version of the new technology, which has special transistor designs for low-leakage levels when circuits are not active. This process is targeted at portable and wireless applications, such as cellular phones, BlueTooth devices and other battery-powered systems.
TSMC said the 0.15-micron technology has created a six-transistor cell measuring 3.422 micron--the smallest in the industry, according to the company. TSMC will offer copper interconnect with a low-k insulator of Fluorinated silicon glass (FSG) for early production partners in the second quarter, said Wu.
Close on the heels of the 0.15-micron copper production, TSMC plans to make available all-copper 0.13-micron technology available for early users. A prototype of the first 0.13-micron copper chips is expected to be taped out for Altera in the second quarter of 2000.
In the fourth quarter, Altera is expected to place a new programmable logic design into copper production using the all-copper 0.15-micron process. In the first half of 2001, the San Jose programmable logic supplier is then expected to move a new product line of 0.13-micron copper devices into TSMC's fabs.
--J. Robert Lineback reporting from the U.S.