FREMONT, Calif. -- Avant! Corp. here has released Cell Verifyer, a tool that enables custom/library cell verification with advanced formal verification techniques at the transistor level by abstracting logical representations from Spice netlists. With it, designers can formally validate transistor-level netlists in minutes, Avant! said.
Traditional verification methods for Spice netlists rely on time-consuming and only partially complete Spice or switch-level simulation. Cell Verifyer uses a very robust transistor extraction technology to extract logical representations for formal equivalence comparison to golden RTL or gate-level models.
Cell Verifyer is an option integrated with Avant!'s Design Verifyer equivalence checker. Together, the systems compare extracted logical representations with their golden RTL and logical models hundreds of times faster than simulation, without test vectors. Because Design Verifyer is based on formal verification technology, and provides 100% coverage, simulation provides only partial coverage and may therefore miss critical bugs, Avant! claimed.
Cell Verifyer is based on transistor-level functional extraction technology developed by Circuit Semantics Inc., a San Jose-based specialist in timing and characterization software. Circuit Semantics' extraction technology enables abstracting logical representations from Spice netlists. Working in partnership with Avant!, the technology was extended enabling its use with formal verification. It handles the full range of static and dynamic design styles including domino, pre-charged, and latching domino to model and verify the most complex CMOS logic.
"We have had excellent feedback from our beta customers," said Chi-Ping Hsu, head of product management at Avant!. "One beta customer, that provides technology for high-speed telecommunication and network applications, using Cell Verifyer formally verified two libraries comprising over 700 cells in just two days, including time to learn the tool. This task would havetaken weeks of effort using simulation and still allowed the possibility of error."
The tight integration of Cell Verifyer with Design Verifyer made it easier to use than simulation, Hsu said. "And they found problems including non-synthesizable constructs and logical differences that simulation wouldn't have found. As a result of verifying the cells so fast, they were able to
make sure their design was accurate before they went to layout."