SAN JOSE--Cadence Design Systems Inc. here reported that the corporate semiconductor development division of Matsushita Electric Industrial Co. Ltd. has selected its Cierto signal-processing worksystem and design tools for system-on-ASIC design flows in communications and multimedia applications.
Cadence said Matsushita will use the signal processing worksystem (SPW) as platform for system algorithm design to register-transfer-level (RTL) implementation. This will reduce the time for design optimization and verification of designs by allowing the C++ algorithm model to be used as the executable system specification, according to Cadence. Cadence's SPW also supports the common design environment between the Matsushita Corporate Semiconductor Development Division and System Division by allowing exchange of IP behavioral models between the two operations.
"The Cierto signal processing worksystem provides the most complete, industry-proven flow from system-level design to hardware implementation of any digital signal processing (DSP) design environment," said Yasuhiro Nakakura, team leader, CE System LSI Development Center in Matsushita's Corporate Semiconductor Development Division. "By using SPW, we will be able to develop advanced consumer electronics product rapidly by having a common design environment between system division and CSDD. For these reasons we will adopt SPW for design of our communications products."
Initially, Matsushita applied SPW to system-on-chip designs for digital television. Using it as a common design platform between the systems division and the corporate chip development division allowed the SPW algorithm models (floating and fixed) to be shared. This has significantly improved system-level verification time and hardware optimization for TV design, according to Matsushita. The signal processing worksystem is also being used to develop SoC devices for digital cameras.