VANCOUVER, B.C. -- PMC-Sierra Inc. here today announced a 2.5-gigabits-per-second (OC-48) channelized architecture that it said will allow for the convergence of traditionally separate voice and data infrastructures into highly integrated carrier-class multi-service networks.
The Chess (Channelizer Engine for Sonet/SDH) chip set architecture allows IP routing, ATM/frame relay switching, Sonet/SDH digital cross connect/add-drop multiplexing, and dense wavelength division multiplexing (DWDM) transport functionality to be built in a single, space-efficient hardware platform.
PMC-Sierra said its technology could revolutionize the way carrier and Internet service provider (ISP) networks are built, deployed and managed. By replacing as many as five or six older, discrete network equipment elements, multi-service equipment networks utilizing the Chess chip set will enable carriers and ISPs to provision a greater number of services more dynamically and at lower cost, the Canadian company said.
The Chess chip set manages scarce Sonet/SDH bandwidth and DWDM lambda wavelengths, which are critical to deploying and operatingf true multi-service networks. These networks can now utilize simplified software management layers making them significantly easier for carriers and ISPs to operate, PMC-Sierra said.
Chess provides Sonet/SDH framing capability at OC-3, OC-12 and OC-48 optical line rates. Its STS-1 channelized traffic grooming capability allows for the development of dedicated service processing cards such as Packet-over-Sonet, ATM and frame relay that replace entire, dedicated network service equipment. Chess' STS-1 grooming capability also will allow for sub-lambda wavelength processing such that multiple user services can be run over individual 2.5 Gbit/s lambda wavelengths.
"The Chess chip set architecture will significantly improve the ability of our customers to provide increased service level provisioning in their next-generation carrier-class equipment," said Steve Perna, PMC-Sierra's vice president and general manager of the Optical Networking Division.
The CHESS chip set consists of five devices, each of which offers industry-leading density and functionality, according to PMC-Sierra, and designed to operate seamlessly together: the Spectra-2488 framer with STS-1/AU3 channelizer; Spectra-4x155 Sonet/SDH framer with STS-1/AU3 channelizer; telecom bus serializer and auto-protection switching (APS) tri-port; a 768 channel STS-1/AU3 cross-connect traffic-groomer transmission switch element; and 48-channel packet-over-Sonet processor and ATM cell processor with 48 channel STS-1 to DS3 asynchronous mapper
All are implemented in low-power 0.18-micron CMOS technology, except the Spectra-4x155, which is in 0.35-micron CMOS.
Pricing in volume quantities is $99 for the PM5310 telecom bus serializer; $324 for the PM5316/SPECTRA-4x155; $395 for the PM5315/SPECTRA-2488; $396 for the PM7390 packet-over-Sonet processor; and $499 for the PM5372 transmission switching element.
The PM5310 and PM5372 will be available in May. Other samples will be available in the subsequent months.