SAN JOSE -- Pericom Semiconductor Corp. here today announced the first two members of its Gunning Transceiver Logic-Plus (GTLP) family, targeted at datacom, telecom, servers, RAID systems and other applications demands for high data throughput on heavily loaded backplanes.
The GTLP6C816 and GTLP16612A devices act as high-speed translators between TTL or low-voltage TTL (LVTTL) logic levels and backplanes operating at GTLP logic levels. GTLP is aderivative of the Gunning Transceiver Logic (GTL) Jedec standard, JESD8-3.
"Increasing a system's bandwidth and data throughput are major challenges facing today's telecom and datacom system designers," said David Duncan, product marketing manager for Pericom. "GTLP devices operating at 66-MHz clock rates with a 128-bit backplane bus can provide up to 1 gigabyte per second of bandwidth. Designers looking to achieve this kind of data throughput will find that GTLP offers an increase in data bandwidth with the added benefits of higher signal
integrity at lower power and EMI than traditional backplane logic."
All devices in Pericom's GTLP portfolio feature reduced signal output swing (less than 1 volt) into a 50-ohm impedance transmission line, tight input threshold levels (50 mV) and output edge-rate control on both the rising and falling edges of the GTLP outputs. These features help reduce line reflections and electromagnetic interference (EMI), while improving overall signal integrity, allowing for high-speed backplane frequencies.
Because of their flow-through pinout, internal edge-rate control, high operating frequency and drive capability, designers can maintain signal integrity while increasing the number of cards serviced on a high-performance backplane. Pericom's GTLP devices also support live insertion or removal without "glitching" data, an important capability for high-availability communications and networking applications.
Pericom's GTLP6C816 is a clock distribution driver providing LVTTL-to-GTLP and GTLP-to-LVTTL clock translation for high performance backplane bus applications. The device incorporates a high-drive (34 mA) 1:2 fan-out clock driver for the LVTTL-to-GTLP direction to drive a heavily loaded backplane and a low drive (12 mA) 1:6 fan-out clock driver in the GTLP-to-LVTTL direction for noise reduction.
The GTLP16612A is an 18-bit universal bus transceiver which can be used as a high speed interface between cards operating at LVTTL or 5V TTL logic levels (A-Port) and a backplane operating at GTLP logic levels (B-Port). This part features a high drive B-Port (50 mA) and increased edge rate control for driving heavy loads with reduced noise and EMI. An integrated bus hold circuit in the A-port allows data flow in transparent, latched, and clocked modes.
The GTLP6C816AL comes in a 24-pin TSSOP package and is priced at $5.56 in quantities of 100 and the GTLP16612AA comes in a 56-pin TSSOP package and is priced at $7.32 in quantities of 100.