SAN JOSE -- Fujitsu Microelectronics Inc. today introduced its 0.11-micron gate-length ASIC process capability, which it said offers the lowest power in the industry, and uses an all-copper interconnect process.
The 0.11-micron technology (0.07 micron L-effective) will be available by the third quarter of 2001.
Other features include shallow trench isolation, chemical-mechanical polishing (CMP), and cobalt silicide (CoSi2) in transistor gate and source/drain. The copper-interconnect process uses five to eight levels of metal and low-k dielectric techniques with a k constant of 2.6.
Initial products developed using this process will support devices with as many as 56 million gates per chip. The gates will be characterized at 0.85 to 1.65 volt, with analog and I/O blocks to be available in both 2.5 and 3.3 V. Densities are twice those of ASICs manufactured using Fujitsu's 0.18-micron process technology, the company said.
"This very deep-submicron technology continues Fujitsu's leadership in one of the technologies driving advanced networking and communications design, as well as digital A/V design," said Ryusuke Hoshikawa, Fujitsu Microelectronics' president and CEO.
"The new ASIC series and technology provide our customers with extremely fast, high-density products with very high pin counts, along with a large array of cell libraries, macros and IP cores. We will be moving aggressively to bring our initial products to our leading customers in Japan and in North America quickly and efficiently," Hoshikawa added.
Fujitsu's first release will be the high density, low power Standard Cell CS91 and the quick TAT (Turn Around Time) Embedded Array CE91 ASIC series designed for high density, highpin count LSI and portable system LSI. Fujitsu also plans an embedded DRAM offering, the CS90DLS, which will provide more than 192 megabits of DRAM for each 100 mm2 area.
Clock frequencies for the embedded DRAM will reach 200 MHz for SDRAM and more than 300 MHz for Fujitsu's FCRAMs (Fast Cycle RAMs). Packaging for the CS91/CE91 series will be in high ball-count and fine ball-pitch flip-chip BGAs.