SAN JOSE, Calif. -- Xilinx Inc. here today announced a new generation of the Virtex architecture that supports designs of 10-million system-gates. The Virtex-II is optimized for rapid migration to 100-nm (0.10-micron) process technology and 500 million-transistor complexity.
The architecture features what the company called "unprecedented" amounts of memory resources and capabilities, new arithmetic resources, enhanced clock management support, and new I/O technology. The first products based on this architecture will be available later this year.
Using eight-layer interconnect and employing copper technology, the enhanced configurable logic block (CLB) structure achieves an unprecedented combination of silicon efficiency, performance, and routability. CLB enhancements include easier look-up table (LUT) cascading, wide fan-in MUXes, deeper distributed RAM, and arbitrary length shift-registers.
The Xilinx Active Interconnect technology, the fourth generation of Xilinx routing, offers high performance to simplify cores implementation and minimize place and route times in 10 million-gate designs, Xilinx said. The architecture delivers consistent performance across a wide range of high fan-out outputs. This tight fan-out versus delay characteristic is critical in maintaining very high performance in multi-million gate designs.
The Alliance Series version 3.1i design flow has built-in enhancements, including modular design for teams of engineers working together, dramatic runtime improvements for timing closure, incremental design flows, and hierarchical floorplanning for designs of up to 10 million gates. The new architecture was designed for easy synthesis and to provide accurate post-synthesis timing results.
Dennis Segers, senior vice president and general manager for the Xilinx Advanced ProductsGroup, said, "We furthered our leadership with the delivery of our version 3.1I software enabling ten million system-gate design. The Virtex-II architecture will be the hardware vehicle for this new density level and beyond."
Virtex-II architecture was engineered with the need for efficient and quick integration of multiple, complex IP building blocks. Xilinx's Smart-IPTM technology, which enables high-performance predictable and parameterizable cores, allows t predictable core performance through relational placement within the IP. In the new Virtex-II architecture, the Xilinx Active Interconnect technology extends this predictability between IP blocks. The interconnect technology in concert with the modular design feature of the software allows multiple IP blocks to be efficiently integrated within mega-gate designs.