SANTA CLARA, Calif. -- Sapphire Design Automation Inc. here announced the availability of NoiseView, a static timing tool that analyzes a post-route, gate-level netlist to determine the effects of data-dependent noise and glitch.
Sapphire said this technique advances the art of static timing analysis from timing signoff into the area of noise signoff.
According to Shashank Goel, Sapphire's president, "NoiseView addresses the need for designers to see a true picture of how their designs perform in the presence of coupling and to understand the impact of coupling on signal integrity and delay so that they can establish methods of avoiding and correcting its impact. NoiseView's unique use of timing windows allows the tool to be both accurate and fast."
Since the increased wire density of submicron SoC design makes coupling unavoidable, Goel explained, submicron noise requires a new type of signoff tool that can analyze noise at the block and full-chip levels. "Static timing verification is an important element of both timing verification and timing closure. However, until NoiseView, no tool provided a signoff view of the impact of data-dependent noise and glitch noise in deep submicron design," he said.
NoiseView's timing analysis is compatible with PrimeTime from Synopsys Inc. It accepts Verilog netlists and standard parasitic formats such as DSPF (coupled) and SPEF. A typical run of 400,000 gates takes approximately one hour on a Sun Microsystems Ultra 10 workstation.
After using NoiseView, designers can use Sapphire's NoiseIT tool to perform physical optimization to eliminate noise.
NoiseView is available now at a unit cost of $75,000.