MUNICH -- Infineon Technologies AG here today rolled out the "Santa Cruz" member of a highly integrated series of read-channel integrated circuits. The 0.25-micron system-on-chip IC supports access speeds up to 500 megabits per second in hard disk drives.
"With the Santa Cruz read-channel IC, we have integrated a high-performance CMOS read-channel with our microcontroller, customer ASIC, and embedded DRAM," said Ruediger Stroh, senior vice president of the Computer & Network Peripherals Group in Munich.
The new read-channel IC also packs an advanced trellis coding scheme for improved bit error rate (BER) performance in inherently noisy environments, according to Infineon. This design produces signal-to-noise-ratio gains of 1.5 db over uncoded extended partial response equalization (EPR4) channels.
Infineon said it has redefined the architecture for read-channel devices to move many functions from the analog domain in traditional designs to the digital domain. For example, the analog-to-digital converter (ADC) and finite impluse response (FIR) filter was removed from the timing loop of the device with a fully-digital timing recovery scheme, said the Munich chip company.
"The Santa Cruz read-channel IC will pave the way for our next generation of integrated read-channel devices," Stroh said. "The company has a timetable to offer additional family member ICs to support the growing demands placed on next generation mass storage drives."
Samples of the read-channel chip are available now. Housed in a 100-pin thin quad flat pack (TQFP), the CMOS chip is priced at $3.40 each in 100,000-piece quantities.