HONOLULU, Hawaii ( ChipWire) -- Intel Corp. plans to roll out different process technologies that better match the power and performance requirements of target markets outside its core PC microprocessor business. At the same time, Intel is pushing its chip design groups to work together more closely to tackle ever-worsening problems with power consumption.
In the future, Intel will probably introduce more than one process technology at a single technology node -- defined by lithography line widths -- as it strengthens its non-PC product portfolio, which now includes digital signal processors, the StrongARM embedded RISC core and flash memory, said Mark Bohr, Intel fellow and director of process architecture and integration at the company's Portland Technology Development Center, located in Hillsboro, Ore.
"You'll probably see more of that from Intel as time goes on and as we move to a broader product range," said Bohr in an interview here at the 2000 Symposium on VLSI Technology. In recent years, the company has pushed into non-PC markets such as networking equipment and cellular phones.
Intel normally develops a core process technology at its Hillsboro center and then transfers it to the company's fabrication facilities. In some cases the process is tweaked by engineering teams at company headquarters in Santa Clara, Calif., Bohr said.
Intel is now using 0.18-micron design rules as its leading-edge process, and plans to move to a 0.13-micron (drawn) process next year. That process technology, which will likely be disclosed this fall, will have a transistor gate length of 0.07-microns. Bohr would not comment on the technology node -- whether 0.10 micron, 0.07 micron or finer -- at which Intel would start offering different process technologies.
Such a move would follow in the footsteps of many ASIC manufacturers, which in recent years have started to offer process variations depending on customer requirements. A mobile phone maker, for example, may opt for a process technology using transistors with a higher threshold voltage, which will reduce standby current at the expense of performance.
But there are limits to how far Intel will go. The company still opposes the use of silicon-on-insulator technology as a way to eke out more performance. Bohr said SOI's advantage will erode with each new process technology spin. This strategy contrasts with that of IBM Microelectronics, which will introduce both a conventional bulk silicon process as well as a high-performance SOI-based process at the 0.13-micron generation.
While SOI has some performance advantages, Bohr said there are still problems related to wafer quality and an assumed loss of transistor switching speeds because of variations in the charge of the process' "floating body." Meanwhile, junction capacitance, which is alleviated in SOI, is becoming less of a problem with each process technology generation, Bohr said.
Bohr said he also sees changes coming in Intel's approach to chip architecture design. There is now a "paradigm shift" in how chip development teams must interact to counter leakage current, which is becoming a bigger problem as transistors get smaller and more numerous.
Until recently, circuit designers could count on process technology teams to scale down the power supply and threshold voltages so they could throw in more transistors to take advantage of the raw speed of a finer process without a second thought.
No more. More transistors may enable more functionality on a single chip, but at the same time power consumption is becoming unbearable. "When you've got lots of transistors leaking nanoamps, it adds up to lots of standby power," Bohr said. "Now there's more impetus for having better chip architecture for CPUs to have good performance but maybe not so many transistors. You don't just slap on transistors for every function. You don't have that luxury anymore."
To respond to the power consumption crisis, Intel's chip development divisions will have to spend more time working together. "Before we followed a simple scaling law and we could all just go on our merry ways," Bohr said. "It's now a common working theme among chip architects, circuit people and process people that power is a limit."