TAIPEI -- Via Technologies Inc. here today disclosed details about its scaleable High-Bandwidth Differential Interconnect (HDIT) architecture for a next-generation chip set supporting double data rate (DDR) memories in PCs and other computer systems.
The first Via Apollo HDIT chip set is scheduled to be available in sample quantities during the first half of 2001. Via Technologies said the new chip set will be implemented for high-end desktop PCs, workstations, and server applications, supporting microprocessors from both Intel Corp. and Advanced Micro Devices Inc.
"It is designed to exceed next-generation, high-bandwidth data traffic requirements within a PC system, but still maintains a flexible system implementation that allows system OEMs to meet different performance and cost requirements in all segments of the PC market," said Tzu-Mu Lin, senior vice president of engineering at Via.
The new architecture places a DDR266 memory interface, AGP4X, and Via's new 512-megabytes-per-second V-Link bus into an HDIT South Bridge for desktop and mobile PC designs. Via said manufacturers of high-end multiprocessor workstations and servers are also supported with the memory interface and AGP port in the HDIT North Bridge, which can be configured for bandwidth rates up to 4.2 GB/sec.
The data transfer rate from the HDIT North Bridge to the AGP port and I/O expansion slots can be increased to speeds of up to 2.1 GB/sec. by configuring the system in HDIT mode and integrating two additional 64-bit HDIT PCI-X companion chips, according to Via.
"The HDIT V-Link is a high efficiency, low latency bus structure with configurable bandwidth ranges to satisfy different segment system I/O requirements," said Eric Chang, director of product marketing for Via. "The 32-bit, 33-MHz PCI bus with a peak bandwidth of 133 MB/sec., is no longer sufficient as the primary bus between the North Bridge and South Bridge and system expansion for advanced PC systems, which are already being equipped with 1-GHz processors.
"Any high-performance system with leading DRAM technology such as DDR SDRAM would be handicapped when paired with a 32-bit/33-MHz PCI South Bridge," Chang added. "The system would not be able to fully benefit from advanced DDR SDRAM because the PCI bus has now become the systembottleneck."