SAN JOSE -- Toshiba Corp. today launched its next-generation ASIC offering, based on an advanced CMOS process technology with drawn gate lengths of 0.11 micron. Toshiba is also expanding its ASIC offering to pursue new high-performance networking applications, along with the company's existing focus on low-power and high-density chip applications.
To address high-performance ASIC designs, Toshiba has developed a 3.2-gigabit-per-second serial I/O function, 12-nanosecond embedded DRAM, and flip-chip ball grid-array packaging technology, which is capable of supporting up to 1,849 contacts. The TC280 ASIC series is also supported by a collection of third-party design tools under Toshiba's MegaGate Timing Driven Flow methodology. The series offers up to seven layers of copper metal interconnect for logic densities up to 209,000 gates/mm2, said the company.
Toshiba is now working with ASIC customers to implement designs in the new CMOS3 process technology, and the Japanese chip maker said it plans to begin ramping volume production of those application-specific ICs by the second quarter of 2001. U.S.-based managers with Toshiba said the new TC280 ASIC series will be fabricated with the industry's most aggressive CMOS technology, using a drawn transistor gate size of 0.11 micron.
"Our CMOS3 process technology fits into the 0.13-micron node of the Semiconductor Industry Association's technology roadmap, based on metal-interconnect and design rules, but the transistor gate has been shrunk down to 0.11 micron," explained Peter Richmond, director of business development at the System IC Business unit of Toshiba America Electronic Components Inc. in San Jose. "Toshiba is a leader in this process technology node and will be one of the first to bring out a shrunk gate at the 0.13 micron node."
Toshiba is offering a variety of embedded memory functions for the TC280 ASICs, including synchronous DRAM, SRAM, and a new 12-ns FA-DRAM (fast access DRAM) that can be used as an SRAM replacement in designs to save die area. Aimed at high-speed networking applications, the FA-DRAM takes up about a fourth the space of SRAM in embedded designs, Richmond said. The FA-DRAM is fabricated with Toshiba's trench process and available in 2- and 4-megabit organizations as well as 256-bit blocks.
The ASIC series' 3.2-Gbit/sec. serializer/deserializer (SerDes) cells are designed to support ASIC designs for 1- and 10-gigabit-per-second Ethernet applications as well as 100- and 200-Mbit-per-second Fibre Channel, 2.5-Gbit/sec. Sonet, and IEEE 1394b systems.