TOKYO ( ChipWire) -- NEC Corp. has developed a 0.13-micron generation process technology that uses a transistor gate measuring less than 0.10 micron, a length many semiconductor makers consider a technological milestone as CMOS transistors become harder to scale.
Besides expected improvements in transistor speed over the 0.13-micron gate-length transistors NEC announced about a year ago, the UX5 process covers some new ground and makes up for some deficiencies of the company's previous UX4 process. These include the use of a dual-damascene, all-copper metal interconnect as well as the reintroduction of embedded DRAM. Moreover, NEC has included an optional low-leakage current library, and has promised to later introduce new ways to keep power consumption to a minimum.
Though about a year from being ready for volume production, NEC claims it has produced stable test chips on the new process and said it will release test libraries for performance verification in November. If all goes as planned, the company will start taking orders for designs in UX5 next May and ship samples by next August. Volume production is slated for November 2001.
NEC is positioning UX5 for customers making high-speed communications and graphics gear, digital consumer electronics or low-power mobile terminals. There will be separate libraries for these three areas.
The high speed CB-130H version of the process uses transistors with 0.095-micron gate length, a measure of the top electrode that traverses the source and drain, and boasts a transistor delay of 9.5 picoseconds. With a 1.2-volt supply voltage, NEC expects it can achieve clock frequencies between 350 MHz and 1 GHz, the company said.
NEC will also provide the same narrow gate-length transistor for devices used in consumer electronics, where integration and small die size carry great weight. With the CB-130M library, NEC claims it can integrate up to 62 million gates in a single device, or 1.9 times more than with UX4, while reaching frequencies up to 350 MHz.
For mobile devices, NEC has fashioned a low power process called the CB-130L that features a less-aggressive 0.13-micron gate length but has a voltage range that can be scaled from 1.2-to-0.9 volts. Reaching frequencies of up to 100 MHz, the transistors can consume 5 nanowatts for each MHz per gate, according to the company.
A new feature of NEC's UX5 process is its use of copper wiring, up to nine layers in all, as the standard wiring method. Previously, NEC did not have the dual-damascene process technology that some consider necessary for integrating copper, and the company only offered copper as an option to aluminum, which is 40 more resistive than copper. NEC now said it can do dual damascene, and will offer copper as a way to offer thinner wires at every metal layer.
Another development that paved the way for copper is the introduction of a low-k (k = 2.9), ladder-oxide inter-dielectric material for UX5. Shifting from silicon dioxide to new low-k materials is considered a must for 0.10-micron generation devices that employ copper, and many companies are still struggling to incorporate them as the 0.13-micron node comes on-stream (see Oct. 20 story). With the copper and low-k combination, NEC said it can reduce wiring pitch by 30% and coupling capacity by 15%.