SAN JOSE ( ChipWire) Cypress Semiconductor Corp. is getting into the field-programmable gate array integration game, starting with parts that will combine physical-layer (PHY) ICs with the company's own FPGA architecture.
The move mirrors the FPGA-ASIC hybrids being marketed by other programmable logic vendors, each of which has developed a program for merging fixed-function silicon intellectual property (IP) with a programmable array. Cypress claims to hold an advantage in already owning both the IP and the FPGA, an angle that is also being worked by Lucent Technologies.
Specifically, Cypress' Infiniband PHY, announced this week, is being groomed for integration with an FPGA in its next generation of production, said Kamal Dalmia, Cypress systems technology manager. The second-generation PHY could be one of several such parts introduced during the next several months, a Cypress spokesman said.
"Typically, a PHY would sit next to an FPGA or some other programmable device, for people to do other logic beyond what's in the physical layer," Dalmia said. By integrating that FPGA, Cypress hopes to save its customers some board space.
FPGA vendors have been developing parts like these for more than a year, amassing their own libraries of IP to be implemented in programmable logic.
But the PHY is a particularly difficult case due to the analog circuitry involved, Dalmia said. "When Xilinx or Altera gets their PHY IP from somebody, it's actually analog blocks that they would have to put beside their FPGA gates," he said. "Even if Xilinx goes out and buys a company and buys IP, it's not a software effort. It would take time for them to create new silicon and validate new silicon."
In fact, Xilinx announced an agreement to purchase RocketChips Inc. this month month to turn that company's IP into high-speed I/O cores optimized for Xilinx's Virtex FPGAs (see Oct. 3 story).
Marketing vice president Deborah Vogt of Mysticom Inc. in Mountain View, Calif., a maker of Ethernet PHY cores, acknowledged that the mixed-signal nature of a PHY makes it trickier to integrate. But that hasn't stopped programmable logic vendors, she said.
"It could be an advantage to somebody who has the knowledge in that area. There are a number of FPGA companies that are looking to acquire that knowledge through licensing or other ways," she said. "We are in discussions or have been in discussions with companies that want to do that."
Familiarity with the mixed-signal parts won't always translate into an advantage, Vogt said. That's particularly true if the FPGAs are being used to get a design to production more quickly, she said, because traditional telecom suppliers' design cycles can be too long for the FPGA to have much of an impact.
"Depending on the market that they're targeting, if there's a long development cycle, it's less of an advantage," Vogt said.
Cypress should be ready to begin announcing its plans for FPGA-integrated devices within the next month, a spokesman said, with a "steady stream" of devices to be announced during the first quarter of 2001. Every PHY at Cypress particularly the Sonet OC-48 (2.5-Gbit/second) device is being considered for such treatment, as are the company's I/O devices, Dalmia said.
The size of the FPGA that is to be integrated with these parts would be "something on the order of our Delta 39K family," probably with a maximum of 200,000 gates, Dalmia said. "What we're seeing in the market is that for a lot of backplane types of applications, that's enough."