SAN JOSE -- Altera Corp. here has release its first programmable-logic devices to use copper for all layers of interconnect.
Rival Xilinx Inc. was the first to announce the use of copper interconnects, in the Virtex-EM device released in late March, but that chip used copper only for the top layers of metal. Altera's Apex 20KC family, due to begin shipping in the first quarter of 2001, will use copper for all metal layers.
The key distinction is that the uppermost metal layers are thicker and don't need the speed boost that copper provides, said Steve Mensor, a director of product marketing at Altera. "Putting copper there has very little tangible benefit," he said.
Mensor said most of the signal routing inside a die occurs at the lower metal layers, meaning that the speed advantages of copper are best exploited there.
Xilinx officials have said the opposite, however, claiming that their studies showed the top two layers to be the most critical in terms of performance. Xilinx executives could not be reached for comment.
Speed is becoming particularly important to FPGA vendors as they continue to push their parts for use in networking, particularly for applications such as high-speed communications signaling, Mensor said.
The Apex 20KC parts also will see heightened performance due to improvements in Altera's Quartus software, company officials said.
The latest version of Quartus, 2000.09, offered a 30% improvement in Apex performance over the previous version, and the upcoming release in January will add an additional 20%, Altera officials said. Densities for the Apex 20KC will range from 100,000 to 1.5 million gates. The devices are being produced in a 0.15-micron CMOS process at foundry Taiwan Semiconductor Manufacturing Co. Ltd.