GARDEN GROVE, Calif. -- Dense-Pac Microsystems Inc. this week rolled out at new three-dimension chip-packaging format that combines digital signal processors with other devices. The new DSP HeLP-Stack is part of a new series of 3-D packages that will combine dissimilar devices in a three-dimensional assembly, said the company.
The new assembly stacks a fixed-point DSP chip from Texas Instruments Inc. with a 4-megabit SRAM (configured 256-K-by-16 bits), and a 10-MHz timing reference device. The 3-D package has a footprint similar to a 144-pin thin-quad flat pack (TQFP), which normally houses the TI processor. Inside the 3-D package, the 4-Mbit SRAM and timing reference device are stacked on top of the DSP.
The Garden Grove company said the new 3-D package will save more than 50% board space in embedded processor applications, such as telecommunication equipment and broadband gear. "By using pre-tested, off-the-shelf semiconductor components, we provide a highly reliable, flexible solution with low risk to the system designer, and significantly improved delivery times," said John Sprint, chief operating officer of Dense-Pac.
Dense-Pac president and CEO Ted Bruce said, "This stacked assembly is a proof of concept and capability demonstration--the first in a series of application-specific standard products we intend to develop." He added that the proprietary stacking technique can be used on many different types of leaded plastic devices, but the company is initially focusing the DSP HeLP-Stack on high-growth market applications demanding smaller space and higher performance.
The initial DSP HeLP-Stack product is available in sample quantities for $150 each.