MELBOURNE, Fla. Qualification chips from a new manufacturing process are currently under evaluation at Harris Semiconductor's production facilities in Palm Bay, Fla., the company said Tuesday (March 30).
The new process, called UHF-2, has been developed to manufacture high-speed data-communications chips to operate in equipment for the 2.4-GHz ISM band, serving several segments of the growing wireless networking market.
UHF-2 is a BiCMOS manufacturing process that will be run in Harris' Fab 59 in Palm Bay. It will provide higher performance transistors, lower power consumption and robust compliance to key parameters allowing for improved receiver sensitivity and range as compared to Harris' current bipolar process, UHF1X. Preliminary testing shows the process achieving transistor performance measured at 25 GHz (fT) and 34 GHz (fmax).
The new process also employs a trench-isolation technique that allows denser packing of transistors on the chip. Smaller die sizes reduce cost and are especially desirable for the small, mobile, battery-operated laptops, PDAs and other such devices that will soon have wireless connectivity.
"For wireless products to proliferate, especially with today's multimedia-heavy content, those products will have to be fast, affordable and not place heavy demands on battery life," said Ron Van Dell, vice president and general manager of Harris Semiconductor's Communications Products Business (Melbourne, Fla.). "The new process Harris is bringing on line will help in each of these areas."
The UHF-2 process includes a suite of high-quality passive components inductors, capacitors, and a low-temperature-coefficient resistors that can be integrated on-chip. Integrating these previously off-chip passive components increases performance and reliability, and reduces a design's bill-of-materials cost.
"This represents a major advancement in our manufacturing technology," Van Dell said. "And, as opposed to buying foundry services, it gives Harris complete control of manufacturing cycle time, feature set, wafer cost, and defect density. Also, the process architecture allows extensions such as addition of silicon germanium SiGe bipolar transistors for the faster performance needed at higher frequencies, and to accommodate lithographic down-scaling of key CMOS feature sizes."
Harris expects to complete qualification of the process by July, and to sample products by the fall. Full production is expected to ramp in the first months of 2000.