DALLAS -- Texas Instruments Inc. here today said it has added a key networking building block to its 0.21-micron TImeBuilder ASIC portfolio for high-speed communications applications using 10/100-megabit-per-second Ethernet. A digital Ethernet physical interface core from MystiCom Ltd. of Israel now can be used to build a system-level chip with "eight, 12, or more Ethernet ports," said Steve Lepkowski, ASIC Wire Business manager at TI.
The MystiPHY110 is initially being offered in TI's 0.21-micron (0.18-micron L-effective) ASIC process, with a 0.18-micron (drawn) version expected to become available next year. MystiCom's PHY core interfaces to either twisted pair or fiber optic cable networks. It conforms to IEEE 802.3, 802.3u, 10BaseT and 100BaseIx physical layer specifications.
"The MystiPHY110 give TI's customers a performance of over 140 meters with power under 300 mW and less than 4 square millimeters per port," said David Almagor, president and CEO of MystiCom.
TI is using a multiple bus ASIC architecture to integrate Ethernet functions with digital signal processors, analog functions, SRAM and a RISC processor. In addition to its own DSP cores, TI is supporting a handful of RISC cores, including architectures from MIPS, ARM, and NEC. The TimeBuilder and MystiPHY110 will offer system-level integration (SLI) from Ethernet cable to the backplane, said Richard Kerslake, SLI business manager at TI.
Design support along with software/hardware co-verification tools will speed up the development of single-chip subsystems, he added. "Our goal is to allow customers to choose a RISC processor, DSP and peripherals, and within a week, allow them to complete a processor subsystem design in RTL register transfer language," Kerslake said.
The MystiPHY110 is scheduled to be available from TI's ASIC product group during the second half of 1999.