BELFAST, Northern Ireland -- Integrated Silicon Systems Ltd. here today announced a development pact with Xilinx Inc. to make available ISS's Reed-Solomon error detection/correction technology for field-programmable gate arrays. New cores will be used in Xilinx Smart-IP technology, which allows FPGA customers to set their own parameters.
Under the development agreement, engineers from Xilinx's operation in Edinburgh, Scotland, with work with ISS developers in Belfast to create high-performance Reed-Solomon encoder and decoder cores for FPGAs. These blocks will be offered in Xilinx's Virtex, Spartan, and XC4000 series of FPGAs.
"Through Xilinx we can reach the broad base of FPGA users worldwide, and with the Smart-IP technology, this new solution addresses a wide variety of user customization requirements," said James G. Dougherty, chief executive officer of ISS. "That allows ISS to continue to work with our partners to develop complex, market-focused application specific virtual components (ASVCs) for next generations systems."
San Jose-based Xilinx said beta versions of the LogiCore Reed-Solomon cores are now being used by FPGA customers, and production versions are slated to be released for Virtex, Spartan and the XC4000 series early next year. The company said a Reed-Solomon decoder configuration takes up 58% of the logic in a 20,000-gate SpartanXL device. That configuration will represent a silicon implementation cost of $3.36 per chip for quantities of 100,000 at the end of next year, Xilinx said.
"We saw that is was time to address the increasing demand by our customer base for Reed-Solomon cores with a cost-effective, easy to use LogiCore solution," said Babak Hedayati, program director for core solutions marketing at Xilinx.