SAN JOSE--Cadence Design Systems Inc. today said it has extended its agreement with ST Microelectronics to supply design automation tools for new ICs with 0.18-micron drawn gate lengths (0.15-micron L effective).
Under the multi-million dollar, multi-year agreement, ST Microelectronics' Central R&D operation in Agrate, Italy, and Grenoble, France, will purchase Cadence software licenses to support its entire design team. Cadence said the agreement covers a wide range of software, including place-and-route, layout automation, design environment, and interactive physical verification.
The exact dollar value of the agreement was not disclosed.
"Collaborative relationships with companies such as Cadence are key to ST Microelectronics maintaining its position as a leading-edge semiconductor manufacturer," said Phillipe Magarshack, design automation and libraries program director at the European chip maker. "Access to the most advanced deep submicron tool suites from Cadence are fundamental to our strategy for keeping our 0.18-micron, 0.15-micron and 0.12-micron design flows under control, and remaining at the forefront of IC design well into the new millennium.
"In the deep submicron world, parasitic effects, such as cross-talk or electromigration, must be prevented during the design process instead of only being analyzed in a post-layout task," he said. "We believe that the work we have done in common with Cadence to this effect will provide a best-in-class EDA solution to this challenge."