OTTAWA, Ontario ( ChipWire/EET) -- The semiconductor group of Mosaid Technologies Inc. is moving into content-addressable memories (CAMs) as the first step toward networking merchant semiconductor products the company plans for the next few years. The Class-IC CAM family will use a DRAM cell for optimal density, power dissipation and scaling, and Mosaid said it expects to move to 32-megabit densities by 2002, and a 0.13-micron CMOS process.
CAMs utilize a search-table concept to look for information and have found their broadest use in routing and packet-classification duties for data networking. The mid-density market, once dominated by Music Semiconductor and Kawasaki LSI, has expanded at higher densities to include new players such as Lara Technologies, NetLogic Microsystems, SiberCore Technologies and other startups.
Dan Mathers, senior vice president and general manager of the semiconductor division at Mosaid, said the company is hardly a stranger to networking applications. Mather's group is helping to design the single-chip encryption processor that Chrysalis-ITS announced at NetWorld+Interop and has its own relationship with ARC Cores Ltd., the company whose RISC cores are used in the Chrysalis project.
Mosaid also has worked with Toshiba Ltd. on a large switching fabric design. The move to CAMs was spurred by the belief that with an appropriate fast search-engine design, the $28 million global market for CAMs in 1998 could soon expand to between $200-$400 million.
"We've had an idea for a DRAM-based CAM cell for several quarters and surveyed users about an appropriate feature set," Mathers said. "Everyone wants to turn from binary to ternary architectures, and DRAM CAM cells give you ternary information for free."
Ternary structures allow for "yes," "no" and "don't care" states for multidimensional classification problems. The shift of Internet Protocol networks toward differentiated services and IP Version 6 fueled the use of ternary CAMs, Mather said; the more complex CAMs were not likely to be appropriate for simple hash tables in Layer 2 switches, he added.
The first fruits of the Mosaid labor are represented in the Class-IC DC2144-15T, a 2-Mbit ternary memory that can be configured as,16K-x-144 bits, 32K-x-72 bits, or 64K-x-36 bits. Mark Roberts, director of technical marketing and applications engineering at Mosaid, said that the 144-bit-wide configuration would be used for IP flow specification, while the 32K-x-72 model would be used in Layer 2/3 switching, and the 36-bit-wide option used for ATM or IP routing.
The memory can handle 66 million searches per second and is capable of processing table sizes greater than 500,000 entries. A special logic block for multiple match resolution, with its own dedicated register set, allows designers to output multiple matches in router and switch designs that accomplish several packet classification tasks in parallel.
While the device is 304 pins, Roberts said every effort was made to conserve pinouts on the memory. The CAM implements a double-data-rate function to clock data on rising and falling edges of a clock, allowing significant reduction of search data pins -- a 72-bit input in one clock cycle needs 36 search pins, while a 144-bit input requires 72 pins.
Auto learning in the CAM is accomplished in one clock cycle. Memory depth can be expanded through the cascading of up to eight memories without glue logic. The CAM has an automatic aging function with separate validity bits for empty, skip, permanent and age. One chip can be partitioned to support up to eight independent databases. An equal number of data mask registers support eight separate masks for data writes, automatic learns and multiple searches.
The DC2144-15T is a 2.5-V/3.3-V, 66-MHz device implemented in 0.25-micron CMOS and packaged in a 304-pin BGA. Sampling starts in November, with full production slated for the first quarter of 2000, when volume pricing will be set.
As Mosaid moves to a 0.18-micron process, it will offer a second-generation 2-Mbit memory at 133 MHz as well as its first 4-Mbit and 8-Mbit memories. By the end of 2001, the move to 0.15-micron CMOS will allow a 16-Mbit memory, followed by a 32-Mbit CAM in late 2002 or early 2003.