SAN JOSE ( ChipWire) -- Microprocessor designers need to adopt fresh techniques and new kinds of metrics to align their work with the coming "post-desktop era," according to John Hennessy, an architect of the first commercial RISC processor and a professor of electrical engineering and computer science at Stanford University.
Requirements for compact, low-power, highly reliable embedded devices and techniques such as multithreading will drive the next generation of processor designs, Hennessy said in a keynote at the Microprocessor Forum.
In a world of smart phones, handheld computers and other network-centric devices, reliability will become increasingly important, Hennessy said. "What's going to happen when everyone depends on computer networks to handle every transaction?", he asked. "We as architects have done little to ask what we can do to reduce the number of system failures. We have to look at new options in reliability and fault containment.
"We can't just look at SPECmarks anymore, but we have to consider area, power, application support and reliability as well," he added. "The most important function is how well does your device's reliability hold up."
Hennessy also cited a looming transition in the techniques employed by chip designers. Current techniques for eking more performance out of microprocessor designs through instruction-level parallelism (ILP) are running out of steam, he said.
"These techniques are getting ever more complicated. I don't see any performance wall, but there are steeper slopes ahead," he said, citing the complexity of using ILP techniques such as trace caching and value speculation. Bigger advances will come as designers embrace parallelism through multithreading, but that requires a significant transition, he said.
"We are entering a domain where designers need to employ multiple threads and that requires software support," he said. "That means we have to help software guys think of new ways to deal with parallelism. It's time we get started on the process of moving to multithreaded software models."
Several papers at the Microprocessor Forum detail architectures that use multithreading or multiple processors on a single chip, including the MAJC processor from Sun Microsystems Inc. and a new general-purpose architecture from Cradle Technologies Inc.
The performance these new techniques gain will no longer be measured in raw MIPS or megahertz as in the desktop PC. Instead, new measures that focus on system-level benefits such as realistic game play and network data rates will be key. "In this Web-centric world information access is the killer app and the network connection is the crucial component," Hennessy said.
But some intractable problems remain on the horizon, Hennessy said. "What really scares me is how big the verification teams are getting," he said. And validation for system-on-chip designs "is a problem we have barely scratched the surface of."
Indeed, the job of designing a microprocessor that once took 15 months now stretches over three years, he said. "It's like rolling a boulder uphill--a boulder that sometimes crushes a design team. This has happened more than once and will happen more frequently as we take on more complex tasks," he said.
Coincidentally, two papers were pulled from the forum at the eleventh hour. ArtX has decided it is not yet ready to detail its graphics processor for the next-generation Nintendo platform, and x86 designer Rise Technology is "revisiting its road map in light of the current landscape," said Michael Slater, founder of MicroDesign Resources and host of the conference (see today's story).